Apparatus and process for pattern distortion detection for semiconductor process and semiconductor device manufactured by use of the apparatus or process

Claim 2

A pattern distortion detecting method in a semiconductor manufacturing process comprising the steps of: forming a predicted finished layout pattern based on a design layout pattern or an inspection layout pattern; converting an outline of said predicted finished layout pattern into a polygon to generate a polygonized predicted finished layout pattern; detecting a pattern distortion in said predicted finished layout pattern by logical figure operation of input data of said polygonized predicted finished layout pattern or of said polygonized predicted finished layout pattern and said design layout pattern or inspection layout pattern; forming a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; forming a plurality of highly-defined predicted finished patterns by performing graphical operations between each of a plurality of said polygonized predicted finished patterns and said design layout patterns or inspection layout patterns; and merging said plurality of highly-defined predicted finished patterns.

Claim 3

The pattern distortion detecting method according to claim 1 , wherein the step of converting the outline of the predicted finished layout pattern into the polygon comprises a substep of reducing the number of apices of the polygonized predicted finished layout pattern.

Claim 4

The pattern distortion detecting method according to claim 1 , wherein the step of detecting a pattern distortion includes a step of forming a test reference layout pattern based on said design layout pattern or a reference layout pattern, and a step of detecting a pattern distortion in said predicted finished layout pattern by comparing said polygonized predicted finished layout pattern with said test reference layout pattern, wherein said step of forming a test reference layout pattern comprises a substep of generating, as the test reference layout pattern, an upper limit test reference layout pattern for defining an allowable upper limit by enlarging the design layout pattern, and a substep of generating, as the test reference layout pattern, a lower limit test reference layout pattern for defining an allowable lower limit by reducing the design layout pattern.

Claim 5

The pattern distortion detecting method according to claim 3 , wherein the substep of generating an upper limit test reference layout pattern generates an upper limit test reference pattern by adding rectangular regions having a predetermined size to the design layout pattern at corner portions thereof and increasing a size of a resulting test reference layout pattern by a pattern distortion allowable amount.

Claim 6

The pattern distortion detecting method according to claim 4 , wherein the size of said rectangular regions is adjusted so that adjacent ones of the rectangular regions do not overlap with each other.

Claim 7

The pattern distortion detecting method according to claim 3 , wherein the substep of generating a lower limit test reference layout pattern generates the lower limit test reference layout pattern by deleting rectangular regions having a predetermined size from the design layout pattern at corner portions thereof and decreasing a size of a resulting test reference layout pattern by a pattern distortion allowable amount.

Claim 8

The pattern distortion detecting method according to claim 6 , wherein the size of the rectangular regions is adjusted so that adjacent ones of the rectangular regions do not overlap with each other.

Claim 9

The pattern distortion detecting method according to claim 1 , further comprising the step of: calculating an amount of the pattern distortion, where the pattern distortion is detected, based on a difference between said design layout pattern or a reference layout pattern and said predicted finished layout pattern.

Claim 10

The pattern distortion detecting method according to claim 1 , wherein the step of detecting a pattern distortion further comprises a step of detecting whether the predicted finished layout pattern shrinks or expands more than the design layout pattern by comparing the polygonized predicted finished layout pattern with a test reference layout pattern.

Claim 11

The pattern distortion detecting method according to claim 1 , further comprising the step of: performing a graphical operation between the pattern distortion of the predicted layout pattern and another design layout layer and selecting pattern distortion information based on pattern distortion information selecting conditions.

Claim 12

The pattern distortion detecting method according to claim 1 , further comprising the steps of: forming a plurality of predicted finished layout patterns to be formed based on a design layout pattern or an inspection layout pattern corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; and obtaining contrast information of the predicted finished pattern based on a difference in pattern between the plurality of predicted finished layout patterns.

Claim 13

The pattern distortion detecting method according to claim 11 , further comprising the step of: detecting a low contrast part of the predicted finished pattern by under-sizing the difference in pattern between the plurality of predicted finished layout patterns.

Claim 14

The pattern distortion detecting method according to claim 1 , further comprising the step of: forming a highly defined polygonized predicted finished pattern by performing graphical operations between said polygonized predicted finished pattern and said design layout pattern or a reference layout pattern based on a finished pattern predicting specification.

Claim 15

The pattern distortion detecting method according to claim 1 , further comprising the steps of: forming a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; and performing graphical operations among a plurality of said polygonized predicted finished patterns to output the result as a predicted finished layout pattern.

Claim 16

A semiconductor device manufactured by a manufacturing process including the pattern distortion detecting method as set forth in claim 1 .

Claim 17

A pattern distortion detecting method comprising the steps of: forming a plurality of predicted finished layout patterns based on a design layout pattern or an inspection layout pattern corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; and performing graphical operation of a plurality of finished predicted patterns to detect differences in regions among a plurality of the finished predicted patterns.

Claim 18

A pattern distortion detecting method comprising the steps of: forming a plurality of predicted finished layout patterns based on a design layout pattern or an inspection layout pattern corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; and performing graphical operation of a plurality of finished predicted patterns to detect differences in regions among a plurality of the finished predicted patterns.

Claim 19

The pattern distortion detecting method according to claim 16 , further comprising the steps of: forming a test reference layout pattern based on a specific one of the predicted finished patterns; comparing each of the predicted finished patterns with said test reference layout pattern to detect a pattern distortion.

Claim 20

The pattern distortion detecting method according to claim 17 , wherein said step of forming a test reference layout pattern includes the substeps of: forming an upper limit test reference layout pattern to define an allowable upper limit larger than the specific predicted finished pattern by a prescribed amount; and forming a lower limit test reference layout pattern to define an allowable lower limit smaller than the specific predicted finished pattern by a prescribed amount.

Claim 21

A pattern distortion detecting apparatus for a semiconductor manufacturing process comprising: finished pattern predicting means for predicting a finished pattern to be formed based on a design layout pattern; predicted finished pattern polygonizing means for converting an outline of the predicted finished pattern into a polygon to generate a polygonized predicted finished pattern; a highly-defined finished pattern predicting means configured to receive a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions, configured to form a plurality of highly-defined predicted finished patterns by performing graphical operations between each of a plurality of said polygonized predicted finished patterns and said design layout patter, and configured to merge said plurality of highly-defined predicted finished patterns, and output a merged highly-defined finished pattern, pattern distortion detecting means for detecting a pattern distortion in the merged highly-defined predicted finished pattern logical figure operation of said merged highly-defined predicted finished pattern and said design layout pattern.

Claim 22

A pattern distortion detecting apparatus for a semiconductor manufacturing process comprising: finished pattern predicting means for predicting a finished pattern to be formed based on a design layout pattern; predicted finished pattern polygonizing means for converting an outline of the predicted finished pattern into a polygon to generate a polygonized predicted finished pattern; a highly-defined finished pattern predicting means configured to receive a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions, configured to form a plurality of highly-defined predicted finished patterns by performing graphical operations between each of a plurality of said polygonized predicted finished patterns and said design layout patter, and configured to merge said plurality of highly-defined predicted finished patterns, and output a merged highly-defined finished pattern, pattern distortion detecting means for detecting a pattern distortion in the merged highly-defined predicted finished pattern logical figure operation of said merged highly-defined predicted finished pattern and said design layout pattern.

Claim 23

A computer program recorded media recording a computer program readable by a computer which enables pattern distortion detection in a semiconductor manufacturing process, said computer program enabling the processing of: forming data of design layout pattern, inspection layout pattern or reference layout pattern in a memory area, forming a predicted finished layout pattern based on a design layout pattern or an inspection layout pattern; converting an outline of said predicted finished layout pattern into a polygon to generate a polygonized predicted finished layout pattern; forming a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; forming a plurality of highly-defined predicted finished patterns by performing graphical operations between each of a plurality of said polygonized predicted finished patterns and said design layout pattern or inspection layout pattern; merging said plurality of highly-defined predicted finished patterns; and detecting a pattern distortion using a highly-defined predicted finished pattern output in said mergings step.

Claim 24

A computer program recorded media recording a computer program readable by a computer which enables pattern distortion detection in a semiconductor manufacturing process, said computer program enabling the processing of: forming data of design layout pattern, inspection layout pattern or reference layout pattern in a memory area, forming a predicted finished layout pattern based on a design layout pattern or an inspection layout pattern; converting an outline of said predicted finished layout pattern into a polygon to generate a polygonized predicted finished layout pattern; forming a plurality of polygonized predicted finished patterns corresponding to a plurality of optical conditions and/or a plurality of pattern forming process conditions; forming a plurality of highly-defined predicted finished patterns by performing graphical operations between each of a plurality of said polygonized predicted finished patterns and said design layout pattern or inspection layout pattern; merging said plurality of highly-defined predicted finished patterns; and detecting a pattern distortion using a highly-defined predicted finished pattern output in said mergings step.