US6154714A
Expired / Lapsed
US
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Method for using wafer navigation to reduce testing times of integrated circuit wafers
Assignee: HEURISTIC PHYSICS LABORATORIES
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Filing: 1997-11-17
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Granted: 2000-11-28
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Expires: 2017-11-17
Abstract
Abstract A method for testing an integrated circuit wafer is described, wherein the wafer has a first plurality of dice defined thereon, and at least one die has at least one known defect. The method comprises the steps of selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to the first die, determining, based upon the analysis, a probability of failure for each known defect on the first die, and modifying the sequence of tests performed on the first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
Inventors
- 👤 David Yepejian Lepejian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:32
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318307
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
119 words
A method for testing an integrated circuit wafer, the wafer having a plurality of dice defined thereon, at least one die having at least one known defect, as determined by inspection, the method comprising the steps of: selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to said first die; determining, based upon said analysis of said connectivity information and said defect information, a probability of failure for each known defect on said first die; and modifying the sequence of tests performed on said first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
Claim 2
Independent Claim
119 words
A method for testing an integrated circuit wafer, the wafer having a plurality of dice defined thereon, at least one die having at least one known defect, as determined by inspection, the method comprising the steps of: selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to said first die; determining, based upon said analysis of said connectivity information and said defect information, a probability of failure for each known defect on said first die; and modifying the sequence of tests performed on said first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
Claim 3
Dependent Claim
52 words
The method of claim 1 wherein said step of analyzing is further defined as including the steps of: dynamically extracting net list information for at least one circuit relating to a defect being analyzed; and determining at least one conductive path likely to be impaired by the at least one known defect.
Claim 4
Dependent Claim
61 words
The method of claim 1 further including the step of: compiling historical test data relating to defect attributes existing on at least one die defined upon at least one wafer; and wherein said analyzing step is further defined as including the step of performing an analysis of said historical test data to determine whether prior similar defects had successfully passed testing.
Claim 5
Dependent Claim
62 words
The method of claim 1 further including the step of: compiling historical inspection data relating to defect attributes on at least one die defined on a wafer; and wherein said analyzing step includes an analysis of said historical inspection data to determine whether past similar defects existing on a second die had resulted in rejecting said second die due to fatal defects.
Claim 6
Dependent Claim
43 words
The method of claim 4 wherein said inspection data includes at least one of the following attributes: the layer most recently deposited prior to a defect being identified, the size of the defect, the location of the defect, whether the defect is conductive.
Claim 7
Dependent Claim
66 words
The method of claim 1 further including the steps of: compiling historical test data relating to at least one defect attribute on a second die on a second wafer; and compiling historical inspection data relating to at least one defect attribute on said second die; and wherein said analyzing step includes an analysis of said historical inspection data and an analysis of said historical test data.
Claim 8
Dependent Claim
44 words
The method of claim 6 wherein said historical inspection data includes at least one of the following attributes: the layer most recently deposited prior to said defect being identified, the size of said defect, the location of the defect, whether said defect is conductive.
Claim 9
Independent Claim
151 words
A method for testing an integrated circuit wafer, the wafer having a first plurality of dice defined thereon, at least one die having at least one known defect, as determined by inspection, the method comprising the steps of: selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to said first die; determining, based upon said analysis of said connectivity information and said defect information, a probability of failure for each known defect existing on said first die; and ranking, on said first die having a plurality of known defects, each known defect in decreasing probability of failure; modifying the sequence of tests performed on said first die so that one or more tests directly relating to said known defects are performed in an order corresponding to the results of said ranking step and prior to performing tests which are unrelated to a defect.
Claim 10
Independent Claim
151 words
A method for testing an integrated circuit wafer, the wafer having a first plurality of dice defined thereon, at least one die having at least one known defect, as determined by inspection, the method comprising the steps of: selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to said first die; determining, based upon said analysis of said connectivity information and said defect information, a probability of failure for each known defect existing on said first die; and ranking, on said first die having a plurality of known defects, each known defect in decreasing probability of failure; modifying the sequence of tests performed on said first die so that one or more tests directly relating to said known defects are performed in an order corresponding to the results of said ranking step and prior to performing tests which are unrelated to a defect.
Claim 11
Independent Claim
113 words
A method for controlling the testing of an integrated circuit wafer, the wafer having a first plurality of subregions defined thereon, at least one subregion within said plurality of subregions having at least one known defect, as determined by inspection, the method comprising the steps of: analyzing connectivity information and defect information relating to the at least one subregion having at least one known defect; determining, based upon said analysis, a probability of failure for each at least one known defect; and rejecting, prior to testing, any of the at least one subregions having at least one known defect if said known defect is determined to have an unacceptably high probability of failure.
Claim 12
Independent Claim
113 words
A method for controlling the testing of an integrated circuit wafer, the wafer having a first plurality of subregions defined thereon, at least one subregion within said plurality of subregions having at least one known defect, as determined by inspection, the method comprising the steps of: analyzing connectivity information and defect information relating to the at least one subregion having at least one known defect; determining, based upon said analysis, a probability of failure for each at least one known defect; and rejecting, prior to testing, any of the at least one subregions having at least one known defect if said known defect is determined to have an unacceptably high probability of failure.
Claim 13
Dependent Claim
52 words
The method of claim 9 wherein said step of analyzing is further defined as including the steps of: dynamically extracting net list information for at least one circuit relating to a defect being analyzed; and determining at least one conductive path likely to be impaired by the at least one known defect.
Claim 14
Dependent Claim
61 words
The method of claim 9 further including the step of: compiling historical test data relating to defect attributes existing on at least one die defined upon at least one wafer; and wherein said analyzing step is further defined as including the step of performing an analysis of said historical test data to determine whether prior similar defects had successfully passed testing.
Claim 15
Dependent Claim
62 words
The method of claim 9 further including the step of: compiling historical inspection data relating to defect attributes on at least one die defined on a wafer; and wherein said analyzing step includes an analysis of said historical inspection data to determine whether past similar defects existing on a second die had resulted in rejecting said second die due to fatal defects.
Claim 16
Dependent Claim
43 words
The method of claim 12 wherein said inspection data includes at least one of the following attributes: the layer most recently deposited prior to a defect being identified, the size of the defect, the location of the defect, whether the defect is conductive.
Claim 17
Dependent Claim
66 words
The method of claim 9 further including the steps of: compiling historical test data relating to at least one defect attribute on a second die on a second wafer; and compiling historical inspection data relating to at least one defect attribute on said second die; and wherein said analyzing step includes an analysis of said historical inspection data and an analysis of said historical test data.
Claim 18
Dependent Claim
44 words
The method of claim 14 wherein said historical inspection data includes at least one of the following attributes: the layer most recently deposited prior to said defect being identified, the size of said defect, the location of the defect, whether said defect is conductive.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |