US5986950A — Use of redundant circuits to improve the reliabil…

Claim 1

Independent Claim 131 words

A method for improving yield and reliability in a manufactured integrated circuit incorporating redundant circuits, comprising the steps of: testing the integrated circuit for defects to identify defective portions of the integrated circuit, wherein the defective portions define a pattern; analyzing the pattern of the defective portions of the integrated circuit by comparing the pattern of the defective portions with a predetermined pattern of an integrated circuit including a latent defect for causing a subsequent failure of the integrated circuit, and identifying non-defective portions of the integrated circuit corresponding to the predetermined pattern of the integrated circuit including the latent defect; replacing the defective portions of the integrated circuit with the redundant circuits; and replacing the non-defective portions of the integrated circuit corresponding to the predetermined pattern with additional redundant circuits.

Claim 2

Independent Claim 131 words

A method for improving yield and reliability in a manufactured integrated circuit incorporating redundant circuits, comprising the steps of: testing the integrated circuit for defects to identify defective portions of the integrated circuit, wherein the defective portions define a pattern; analyzing the pattern of the defective portions of the integrated circuit by comparing the pattern of the defective portions with a predetermined pattern of an integrated circuit including a latent defect for causing a subsequent failure of the integrated circuit, and identifying non-defective portions of the integrated circuit corresponding to the predetermined pattern of the integrated circuit including the latent defect; replacing the defective portions of the integrated circuit with the redundant circuits; and replacing the non-defective portions of the integrated circuit corresponding to the predetermined pattern with additional redundant circuits.

Claim 3

Dependent Claim 39 words

The method of claim 1 wherein the non-defective portions of the integrated circuit corresponding to the predetermined pattern are replaced with the additional redundant circuits after the defective portions of the integrated circuit are replaced with the redundant circuits.

Claim 4

Dependent Claim 43 words

The method of claim 1 wherein the testing further includes identifying portions of the predetermined pattern which correspond to the defective portions of the integrated circuit and identifying portions of the predetermined pattern which correspond to the non-defective portions of the integrated circuit.

Claim 5

Dependent Claim 33 words

The method of claim 3 which further includes the step of replacing the portions of the predetermined pattern which correspond to the non-defective portions of the integrated circuit with the additional redundant circuits.

Claim 6

Dependent Claim 42 words

The method of claim 1 wherein the non-defective portions of the integrated circuit which correspond to the predetermined pattern are replaced with the additional redundant circuits which remain available after replacing the defective portions of the integrated circuit with the redundant circuits.

Claim 7

Dependent Claim 38 words

The method of claim 5 wherein sufficient redundant circuits are available for replacing the non-defective portions of the integrated circuit, and wherein all of the non-defective portions of the integrated circuit are replaced with the additional redundant circuits.

Claim 8

Dependent Claim 39 words

The method of claim 5 wherein insufficient redundant circuits are available for replacing the non-defective portions of the integrated circuit, and wherein only some of the non-defective portions of the integrated circuit are replaced with the additional redundant circuits.

Claim 9

Dependent Claim 30 words

The method of claim 1 wherein the integrated circuit is a semiconductor memory circuit including a plurality of memory cells, and wherein the testing includes testing of the memory cells.

Claim 10

Dependent Claim 35 words

The method of claim 8 wherein the defective memory cells are associated with a defective bit line, and which further includes the step of replacing a non-defective bit line adjacent to the defective bit line.

Claim 11

Dependent Claim 46 words

The method of claim 9 wherein the defective memory cells are associated with first and second defective bit lines separated by a non-defective bit line, and which further includes the step of replacing the non-defective bit line located between the first and second defective bit lines.

Claim 12

Dependent Claim 23 words

The method of claim 9 which further includes the step of replacing a plurality of non-defective bit lines surrounding the defective bit line.

Claim 13

Dependent Claim 35 words

The method of claim 8 wherein the defective memory cells are associated with a defective word line, and which further includes the step of replacing a non-defective word line adjacent to the defective word line.

Claim 14

Dependent Claim 29 words

The method of claim 8 wherein the defective memory cells are located in a cluster, and which further includes the step of replacing non-defective memory cells surrounding the cluster.

Claim 15

Dependent Claim 28 words

The method of claim 13 wherein all of the non-defective memory cells surrounding the cluster are replaced, forming a ring of replaced, non-defective memory cells surrounding the cluster.

Claim 16

Dependent Claim 24 words

The method of claim 14 which further includes the step of replacing a plurality of rings of the non-defective memory cells surrounding the cluster.

Claim 17

Dependent Claim 94 words

A manufactured integrated circuit of improved yield and reliability which comprises an operative circuit including non-defective portions, and redundant circuits for replacing defective portions of the operative circuit, wherein the defective portions of the integrated circuit correspond to a predetermined pattern of an integrated circuit including a latent defect for causing a subsequent failure of the integrated circuit, wherein the predetermined pattern includes portions which correspond to the non-defective portions of the integrated circuit, and wherein the non-defective portions of the integrated circuit corresponding to the predetermined pattern are replaced with additional redundant circuits.

Claim 18

Dependent Claim 94 words

A manufactured integrated circuit of improved yield and reliability which comprises an operative circuit including non-defective portions, and redundant circuits for replacing defective portions of the operative circuit, wherein the defective portions of the integrated circuit correspond to a predetermined pattern of an integrated circuit including a latent defect for causing a subsequent failure of the integrated circuit, wherein the predetermined pattern includes portions which correspond to the non-defective portions of the integrated circuit, and wherein the non-defective portions of the integrated circuit corresponding to the predetermined pattern are replaced with additional redundant circuits.

Claim 19

Dependent Claim 29 words

The manufactured integrated circuit of claim 16 wherein all of the non-defective portions of the integrated circuit corresponding to the predetermined pattern are replaced with the additional redundant circuits.

Claim 20

Dependent Claim 30 words

The manufactured integrated circuit of claim 16 wherein only some of the non-defective portions of the integrated circuit corresponding to the predetermined pattern are replaced with the additional redundant circuits.

Claim 21

Dependent Claim 22 words

The manufactured integrated circuit of claim 16 wherein the integrated circuit is a semiconductor memory circuit including a plurality of memory cells.

Claim 22

Dependent Claim 42 words

The manufactured integrated circuit of claim 19 wherein defective memory cells are associated with a defective bit line, and wherein the defective bit line and a non-defective bit line adjacent to the defective bit line are replaced with the additional redundant circuits.

Claim 23

Dependent Claim 44 words

The manufactured integrated circuit of claim 20 wherein the defective memory cells are associated with first and second defective bit lines separated by a non-defective bit line, and wherein the non-defective bit line located between the first and second defective bit lines is replaced.

Claim 24

Dependent Claim 21 words

The manufactured integrated circuit of claim 20 wherein a plurality of non-defective bit lines surrounding the defective bit line are replaced.

Claim 25

Dependent Claim 42 words

The manufactured integrated circuit of claim 19 wherein defective memory cells are associated with a defective word line, and wherein the defective word line and a non-defective word line adjacent to the defective word line are replaced with the additional redundant circuits.

Claim 26

Dependent Claim 26 words

The manufactured integrated circuit of claim 19 wherein defective memory cells are located in a cluster, and wherein non-defective memory cells surrounding the cluster are replaced.

Claim 27

Dependent Claim 30 words

The manufactured integrated circuit of claim 24 wherein all of the non-defective memory cells surrounding the cluster are replaced, forming a ring of replaced, non-defective memory cells surrounding the cluster.

Claim 28

Dependent Claim 22 words

The manufactured integrated circuit of claim 25 wherein a plurality of rings of the non-defective memory cells surrounding the cluster are replaced.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-11-15	2003-05-17	2003-11-16	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-11-15	2007-05-17	2007-11-16	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-11-15	2011-05-17	2011-11-16	$7700.00	Window Closed / Lapsed

Use of redundant circuits to improve the reliability of an integrated circuit

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