US5298433A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for testing semiconductor devices
Assignee: Toshiba Corp
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Filing: 1991-12-26
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Granted: 1994-03-29
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Expires: 2011-12-26
Abstract
Abstract A method for manufacturing semiconductor devices according to this invention, comprises the wafer manufacturing step of forming an integrated circuit with a redundant circuit in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in the integrated circuit for each of the chip areas or for every certain number of the chip areas, the step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with the stress testing terminal in contact with a contact terminal of a tester in the wafer state, the step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through die sort test, the step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of the redundant circuit, and the assembly step of, after the remedying step, separating the chip areas into individual elements and then assembling them into an integrated circuit device.
Inventors
- 👤 Tohru Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:01
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/2872; G01R31/2879; G01R31/30; G01R31/282; G01R31/2831; G01R31/2884; G01R31/2856; Y; Y10; Y10S; Y10S148/00; Y10S148/162
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
193 words
A method for manufacturing semiconductor devices, comprising: a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in said integrated circuit for each of the chip areas; a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a contact terminal of a tester in the wafer state; a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through test; a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit device.
Claim 2
Independent Claim
193 words
A method for manufacturing semiconductor devices, comprising: a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in said integrated circuit for each of the chip areas; a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a contact terminal of a tester in the wafer state; a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through test; a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit device.
Claim 3
Dependent Claim
42 words
A method for manufacturing semiconductor devices according to claim 1, further comprising a step of selecting chips to which a voltage stress is to be applied for failure screening, this step being located between said wafer manufacturing step and failure screening step.
Claim 4
Dependent Claim
28 words
A method for manufacturing semiconductor devices according to claim 1, further comprising a step of screening failures caused in said assembly step in the package state after assembly.
Claim 5
Dependent Claim
28 words
A method for manufacturing semiconductor devices according to claim 2, further comprising a step of screening failures caused in said assembly step, in the package state after assembly.
Claim 6
Independent Claim
60 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said integrated circuit is a memory circuit having a memory cell and a cell peripheral circuit, and performs said screening of failures in said memory cell and the screening of failures in said cell peripheral circuit in the package state after said assembly step.
Claim 7
Independent Claim
63 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said integrated circuit contains a circuit designed so as to be more active or more subjected to stress than during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal or stress voltage via said stress testing terminals.
Claim 8
Independent Claim
58 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said specified interconnections are directly or indirectly connected in common to all of or more than the interconnections selectively activated during normal operation in the finished product state, and are externally applied with a desired stress voltage via said stress testing terminal.
Claim 9
Dependent Claim
35 words
A method for manufacturing semiconductor devices according to claim 7, wherein said interconnections selectively activated during normal operation are interconnections selectively activated by the signal decoded from the address signal or by the scanning signal.
Claim 10
Dependent Claim
55 words
A method for manufacturing semiconductor devices according to claim 8, wherein said chip area is a memory chip area or a memory-incorporated chip area containing a memory circuit, and said interconnections connected in common to said specified interconnections are the word lines and/or bit lines of the memory cell array in said integrated circuit area.
Claim 11
Independent Claim
99 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said chip area contains a step-up circuit that steps up the power supply voltage input and supplies the stepped-up output only to some of the circuits during normal operation in the finished product state, and a control circuit that causes said step-up circuit to reduce the potential of the stepped-up output, make it equal to the potential before the step-up, or stop the step-up operation when said specified interconnections are externally applied with the stress testing control signal via said stress testing terminal.
Claim 12
Dependent Claim
40 words
A method for manufacturing semiconductor devices according to claim 10, wherein said chip area is a dynamic memory chips area or a memory-incorporated chip area containing a dynamic memory circuit, and said step-up circuit is a word-line voltage step-up circuit.
Claim 13
Independent Claim
93 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said chip area is a memory chip area or a memory incorporated chip area containing a memory circuit, which has a refresh address counter and a control circuit that controls said address counter so that the word lines of the memory cell array may be more active than in a refreshing action during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal via said stress testing terminal.
Claim 14
Independent Claim
47 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein a certain number of said stress testing terminals are provided for each of said chip areas, in such a manner that they concentrate almost along one side of the chip area.
Claim 15
Independent Claim
37 words
A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said semiconductor wafer is a semiconductor substrate or a substrate in which a semiconductor layer is formed on an insulating layer.
Claim 16
Independent Claim
191 words
A method for manufacturing semiconductor devices, comprising: a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming a stress testing terminal that applies a stress testing voltage or stress testing signal to interconnections other than those for power supply in said integrated circuit for every certain number of said chip areas; a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a terminal of a tester in the wafer state; a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through a test; a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit.
Claim 17
Independent Claim
191 words
A method for manufacturing semiconductor devices, comprising: a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming a stress testing terminal that applies a stress testing voltage or stress testing signal to interconnections other than those for power supply in said integrated circuit for every certain number of said chip areas; a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a terminal of a tester in the wafer state; a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through a test; a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit.
Claim 18
Dependent Claim
46 words
The method for manufacturing semiconductor devices according to claim 15, further comprising a pre-die sort step of selecting chips to which a voltage stress is to be applied for failure screening, the pre-die sort step occurring between the wafer manufacturing step and the failure screening step.
Claim 19
Dependent Claim
28 words
The method for manufacturing semiconductor devices according to claim 15, further comprising a step of screening failures caused in the assembly step in the package state after assembly.
Claim 20
Dependent Claim
27 words
The method for manufacturing devices according to claim 16, further comprising a step of screening failures caused in the assembly step in the package state after assembly.
Claim 21
Independent Claim
58 words
The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said integrated circuit is a memory circuit having a memory cell and a cell peripheral circuit, and performs the screening of failures in said memory cell and the screening of failures in said cell peripheral circuit in the package stage after the assembly step.
Claim 22
Independent Claim
61 words
The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said integrated circuit contains a circuit designed so as to be more active or more subjected to stress than during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal or stress voltage via said stress testing terminals.
Claim 23
Independent Claim
55 words
The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said specified interconnections are directly or indirectly connected in common to all or more than the interconnections selectively activated during normal operation in the finished product state, and are externally applied with a desired stress voltage via said stress testing terminal.
Claim 24
Dependent Claim
35 words
The method for manufacturing semiconductor devices according to claim 21, wherein said interconnections selectively activated during normal operation are interconnections selectively activated by a signal decoded from an address signal or by a scanning signal.
Claim 25
Dependent Claim
54 words
The method for manufacturing semiconductor devices according to claim 22, wherein said chip area is a memory chip area or a memory-incorporated chip area containing a memory circuit, and said interconnections connected in common to said specified interconnections are word lines and/or bit lines of the memory cell array in said integrated circuit area.
Claim 26
Independent Claim
97 words
The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said chip area contains a step-up circuit that steps up the power supply voltage input and supplies the stepped-up output only to some of the circuits during normal operation in the finished product state, and a control circuit that causes said step-up circuit to reduce the potential of the stepped-up output, make it equal to the potential before the step-up, or stop the step-up operation when said specified interconnections are externally applied with the stress testing control signal via said stress testing terminal.
Claim 27
Dependent Claim
41 words
The method for manufacturing semiconductor devices according to claim 24, wherein said chip area is a dynamic memory chip area or a memory-incorporated chip area containing a dynamic memory circuit, and said step-up circuit is a word line voltage step-up circuit.
Claim 28
Independent Claim
90 words
The method of manufacturing semiconductor devices according to any one of claims 15-18, wherein said chip area is a memory chip area or a memory-incorporated chip area containing a memory circuit, which has a refresh address counter and a control circuit that controls said address counter so that the word lines of the memory cell array may be more active than in a refreshing action during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal via said stress testing terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-28 | 1997-09-27 | 1998-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-28 | 2001-09-27 | 2002-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-28 | 2005-09-27 | 2006-03-29 | $7700.00 | Window Closed / Lapsed |