MIM capacitor having reduced capacitance error and phase rotation

Claim 1

An MIM capacitor for a semiconductor integrated circuit device comprising: a semiconductor substrate; a first insulating film formed on said semiconductor substrate; a lower electrode formed on said first insulating film; a second insulating film formed on said lower electrode; a first opening which penetrates said second insulating film and which reaches said lower electrode; a capacitor insulating film formed on a portion of said lower electrode exposed by said first opening; an upper electrode formed on said capacitor insulating film; a third insulating film formed on said second insulating film and said upper electrode; a second opening which penetrates said second and third insulating films and which reaches said lower electrode; a first lead electrode which fills said second opening, which connects to a portion of said lower electrode exposed via said second opening, and which is drawn out onto the surface of said third insulating film; a third opening which penetrates said third insulating films and which reaches said upper electrode; and a second lead electrode which fills said third opening, which connects to a portion of said upper electrode exposed via said third opening, and which is drawn out onto the surface of said third insulating film; wherein first lead electrode is continuously formed such that said first electrode surrounds at least three sides of said capacitor insulating film, and the width of said capacitor insulating film satisfies the following formula: H<(A/F) ½ where, H designates the width of said capacitor insulating film, A designates a predetermined constant determined depending on a structure and a manufacturing process of said MIM capacitor to obtain desired admittance characteristics, and F designates maximum frequency of a signal used by said MIM capacitor.