Patent US20030165615A1 successfully refreshed from Google Patents.
Patent US6326260B1 successfully refreshed from Google Patents.
US6326260B1
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Gate prespacers for high density, high performance DRAMs
Assignee: International Business Machines Corp
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Filing: 2000-06-22
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Granted: 2001-12-04
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Expires: 2020-06-22
Abstract
Abstract A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.
Inventors
- 👤 Ramachandra Divakaruni
- 👤 James William Adkisson
- 👤 Mary Elizabeth Weybright
- 👤 Scott Halle
- 👤 Jeffrey Peter Gambino
- 👤 Heon Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; H10B12/02; H10B12/05
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
280 words
A method of forming a gate conductor useful in a semiconductor memory device comprising the steps of: (a) providing a semiconductor structure including at least a gate oxide layer formed on a surface of a semiconductor substrate, said structure being divided into array regions and support regions which may have different oxide thicknesses; (b) forming a gate stack on said structure, said gate stack including a layer of polysilicon formed on the gate oxide layer, a conductor material layer formed on said layer of polysilicon, and a nitride cap layer formed on said conductor material layer; (c) partially mask open etching the gate stack by patterning the nitride cap layer and etching through the gate stack stopping on said layer of polysilicon; (d) forming spacers on exposed sidewalls of said partially etched gate stack; (e) completing said mask open etching in said array regions by removing any exposed polysilicon, while not etching said layer of polysilicon in the support regions; (f) performing a first oxidation step on the structure so as to form an oxide layer on exposed polysilicon sidewalls in said array regions while simultaneously forming a sacrificial oxide layer on said layer of polysilicon in said support regions; (g) selectively removing said spacers in said support regions of said structure; (h) selectively removing said sacrificial oxide layer and said layer of polysilicon in said support regions; and (i) performing a second oxidization step on said structure so as to form an array oxide layer and a support oxide layer, said array oxide layer having a thickness that is greater than the support oxide layer, said array oxide layer comprising oxide layers from said first and second oxidation steps.
Claim 2
Independent Claim
280 words
A method of forming a gate conductor useful in a semiconductor memory device comprising the steps of: (a) providing a semiconductor structure including at least a gate oxide layer formed on a surface of a semiconductor substrate, said structure being divided into array regions and support regions which may have different oxide thicknesses; (b) forming a gate stack on said structure, said gate stack including a layer of polysilicon formed on the gate oxide layer, a conductor material layer formed on said layer of polysilicon, and a nitride cap layer formed on said conductor material layer; (c) partially mask open etching the gate stack by patterning the nitride cap layer and etching through the gate stack stopping on said layer of polysilicon; (d) forming spacers on exposed sidewalls of said partially etched gate stack; (e) completing said mask open etching in said array regions by removing any exposed polysilicon, while not etching said layer of polysilicon in the support regions; (f) performing a first oxidation step on the structure so as to form an oxide layer on exposed polysilicon sidewalls in said array regions while simultaneously forming a sacrificial oxide layer on said layer of polysilicon in said support regions; (g) selectively removing said spacers in said support regions of said structure; (h) selectively removing said sacrificial oxide layer and said layer of polysilicon in said support regions; and (i) performing a second oxidization step on said structure so as to form an array oxide layer and a support oxide layer, said array oxide layer having a thickness that is greater than the support oxide layer, said array oxide layer comprising oxide layers from said first and second oxidation steps.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein said gate oxide layer is formed by a thermal growing process or a deposition process selected from the group consisting of CVD, plasma-assisted CVD, sputtering and evaporation.
Claim 4
Dependent Claim
31 words
The method of claim 1 wherein said gate stack is formed by the same or different deposition process selected from the group consisting of CVD, plasma-assisted CVD, plating, sputtering and evaporation.
Claim 5
Dependent Claim
24 words
The method of claim 1 wherein an optional barrier layer is formed on said layer of polysilicon prior to forming said conductor material layer.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein said layer of polysilicon is doped by an in-situ deposition doping process or deposition followed by implantation.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein step (c) includes lithography and etching.
Claim 8
Dependent Claim
14 words
The method of claim 1 wherein said spacers are formed by deposition and etching.
Claim 9
Dependent Claim
12 words
The method of claim 7 wherein said etching occurs during step (e).
Claim 10
Dependent Claim
13 words
The method of claim 1 wherein step (e) includes an anisotropic etching process.
Claim 11
Dependent Claim
25 words
The method of claim 1 wherein said first oxidation step is carried out at a temperature of greater than 850° C. in an oxidizing ambient.
Claim 12
Dependent Claim
21 words
The method of claim 10 wherein said first oxidation step is carried out at a temperature of greater than 900° C.
Claim 13
Dependent Claim
16 words
The method of claim 1 wherein step (g) includes the use of an isotropic etch process.
Claim 14
Dependent Claim
25 words
The method of claim 1 wherein said second oxidation step is carried out at a temperature of greater than 850° C. in an oxidizing ambient.
Claim 15
Dependent Claim
21 words
The method of claim 13 wherein said second oxidation step is carried out at a temperature of greater than 900° C.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-03 | 2005-06-04 | 2005-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-03 | 2009-06-04 | 2009-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-03 | 2013-06-04 | 2013-12-04 | $7700.00 | Window Closed / Lapsed |