US5950091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
Assignee: Advanced Micro Devices Inc
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Filing: 1996-12-06
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Granted: 1999-09-07
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Expires: 2016-12-06
Abstract
Abstract A gate conductor structure and method for forming the structure are provided whereby the overall gate length can be made with less susceptibility to lithography variations. The gate conductor is produced by defining a sidewall surface region and then forming the gate conductor material on that sidewall surface a closely controlled, defined lateral distance therefrom. The gate conductor length is therefore dependent primarily upon deposition technology rather than both deposition and lithography. Deposition can be controlled at the defined sidewall surface more closely than mask alignment, thin film development and etching processes of conventional designs. The gate conductor is formed from the sidewall surface such that the sidewall surface demonstrates a greater likelihood of forming a thicker sidewall spacer on one surface of the gate conductor than the opposing gate conductor surface. Accordingly, the gate conductor demonstrates asymmetrical sidewall spacer formation and the benefits of a drain area formed a greater distance from the channel than a source area.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/01326; H10D64/0133; H10D64/021
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
231 words
A method for forming a transistor, comprising: patterning a sacrificial material having opposed sidewall surfaces upon a dielectric-covered semiconductor substrate; forming a gate conductor upon only said sidewall surfaces; removing a portion of said gate conductor and said sacrificial material; depositing dopants of a first concentration immediately adjacent said gate conductor to form lightly doped drain areas within said semiconductor substrate; forming a first spacer comprising a first thickness and a second spacer comprising a second thickness greater than said first thickness on opposed lateral surfaces of said gate conductor, wherein said first spacer is formed adjacent an arcuate surface of said gate conductor and wherein said second spacer is formed adjacent a planar surface of said gate conductor; depositing dopants of a second concentration greater than the first concentration spaced from said gate conductor by said first spacer and said second spacer to form a source area and a drain area, respectively, within said semiconductor substrate; forming a third spacer and a fourth spacer adjacent said first and second spacers, respectively, wherein a thickness of said third spacer is less than a thickness of said fourth spacer; and depositing dopants of a third concentration spaced from said gate conductor by said third spacer and said fourth spacer to form second source and drain areas, respectively, within said semiconductor substrate; and forming transistor interconnect regions upon the source and drain areas.
Claim 2
Independent Claim
231 words
A method for forming a transistor, comprising: patterning a sacrificial material having opposed sidewall surfaces upon a dielectric-covered semiconductor substrate; forming a gate conductor upon only said sidewall surfaces; removing a portion of said gate conductor and said sacrificial material; depositing dopants of a first concentration immediately adjacent said gate conductor to form lightly doped drain areas within said semiconductor substrate; forming a first spacer comprising a first thickness and a second spacer comprising a second thickness greater than said first thickness on opposed lateral surfaces of said gate conductor, wherein said first spacer is formed adjacent an arcuate surface of said gate conductor and wherein said second spacer is formed adjacent a planar surface of said gate conductor; depositing dopants of a second concentration greater than the first concentration spaced from said gate conductor by said first spacer and said second spacer to form a source area and a drain area, respectively, within said semiconductor substrate; forming a third spacer and a fourth spacer adjacent said first and second spacers, respectively, wherein a thickness of said third spacer is less than a thickness of said fourth spacer; and depositing dopants of a third concentration spaced from said gate conductor by said third spacer and said fourth spacer to form second source and drain areas, respectively, within said semiconductor substrate; and forming transistor interconnect regions upon the source and drain areas.
Claim 3
Dependent Claim
36 words
The method as recited in claim 1, wherein said forming a gate conductor comprises depositing a polycrystalline material upon the gate conductor and thereafter removing the polycrystalline material except in regions immediately adjacent said sidewall surfaces.
Claim 4
Dependent Claim
43 words
The method as recited in claim 1, further comprising, after said patterning and before said forming said gate conductor, removing dielectric from said dielectric-covered semiconductor substrate immediately adjacent said sacrificial material and thereafter growing an oxide in the regions removed of said dielectric.
Claim 5
Dependent Claim
25 words
The method as recited in claim 1, wherein said removing comprises selectively removing the portion of said gate conductor prior to removing said sacrificial material.
Claim 6
Dependent Claim
26 words
The method as recited in claim 1, wherein said removing comprises lithography removing a defined length within a contiguous, laterally extending run of said gate conductor.
Claim 7
Dependent Claim
25 words
The method as recited in claim 1, wherein depositing dopants of said first and said second concentrations comprises implanting n-type species into said semiconductor substrate.
Claim 8
Dependent Claim
25 words
The method as recited in claim 1, wherein depositing dopants of said first and said second concentrations comprises implanting p-type species into said semiconductor substrate.
Claim 9
Dependent Claim
69 words
The method as recited in claim 1 wherein removing a portion of said gate conductor and said sacrificial material comprises: depositing a photoresist across said sacrificial material and said gate conductor; patterning said photoresist to expose a portion of said sacrificial material and to expose said gate conductor laterally adjacent said portion of said sacrificial material; etching said exposed gate conductor; removing said photoresist; and etching said sacrificial material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |