Patent US6326218B1 successfully refreshed from Google Patents.
US6326218B1
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Semiconductor integrated circuit and its manufacturing method
Assignee: Hitachi Ltd
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Filing: 2000-05-22
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Granted: 2001-12-04
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Expires: 2020-05-22
Abstract
Abstract Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.
Inventors
- 👤 Takashi Yunogami
- 👤 Kazuo Nojiri
- 👤 Yuzuru Ohji
- 👤 Sukeyoshi Tsunekawa
- 👤 Masahiko Hiratani
- 👤 Yuichi Matsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:34
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/71; H10B; H10B53/00; H10B53/30; H10B53/40; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/682
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
183 words
A manufacturing method of a semiconductor integrated circuit, comprising the steps of: (a) forming, over the main surface of an integrated circuit wafer, a conductive first film which constitutes a lower electrode of an information storage capacitive element of a memory cell, (b) forming, over said first film, a second film having a smaller etching rate than said first film in an ashing atmosphere in a removing step of a photoresist film, (c) forming an inorganic third film over said second film, (d) forming a photoresist film pattern over said third film, (e) dry etching said third film in the presence of said photoresist film pattern, thereby forming an inorganic film pattern of said third film over said second film, (f) removing said photoresist film pattern by ashing, (g) dry etching said first and second films in the presence of said inorganic film pattern, thereby patterning said first and second films, and (h) forming, over the patterned surfaces of said first and second films, a dielectric film which constitutes a capacitive insulating film of the information storage capacitive element of said memory cell.
Claim 2
Dependent Claim
183 words
A manufacturing method of a semiconductor integrated circuit, comprising the steps of: (a) forming, over the main surface of an integrated circuit wafer, a conductive first film which constitutes a lower electrode of an information storage capacitive element of a memory cell, (b) forming, over said first film, a second film having a smaller etching rate than said first film in an ashing atmosphere in a removing step of a photoresist film, (c) forming an inorganic third film over said second film, (d) forming a photoresist film pattern over said third film, (e) dry etching said third film in the presence of said photoresist film pattern, thereby forming an inorganic film pattern of said third film over said second film, (f) removing said photoresist film pattern by ashing, (g) dry etching said first and second films in the presence of said inorganic film pattern, thereby patterning said first and second films, and (h) forming, over the patterned surfaces of said first and second films, a dielectric film which constitutes a capacitive insulating film of the information storage capacitive element of said memory cell.
Claim 3
Dependent Claim
46 words
A manufacturing method of a semiconductor integrated circuit according to claim 1 , wherein said first film is made of ruthenium and said second film is made of any material selected from platinum, ruthenium dioxide, tantalum oxide, titanium oxide, BST, silicon oxide, iridium or iridium dioxide.
Claim 4
Dependent Claim
100 words
A manufacturing method of a semiconductor integrated circuit according to claim 2 , which further comprises: (i) forming, over said capacitive insulating film, a monolayer or multilayer conductive fourth film which is made of, at at least the surface portion thereof, a material having a smaller etching rate than said first film in the ashing atmosphere upon removal of the photoresist film, (j) forming a photoresist film pattern over said fourth film, (k) dry etching said fourth film in the presence of said photoresist film pattern, thereby patterning said fourth film, and (l) removing said photoresist film pattern by ashing.
Claim 5
Dependent Claim
40 words
A manufacturing method of a semiconductor integrated circuit according to claim 3 , wherein said fourth film is formed of a lower layer made of ruthenium and an upper layer made of titanium nitride, a silicon oxide or tantalum oxide.
Claim 6
Dependent Claim
134 words
A manufacturing method of a semiconductor integrated circuit according to claim 2 , which further comprises: (i) forming, over said capacitive insulating film, a monolayer or multilayer fourth conductive film which is made of, at at least the surface thereof, a material having a smaller etching rate than said first film in the ashing atmosphere of a removing step of a photoresist film, (j) forming an inorganic fifth film over said fourth film, (k) forming a photoresist film pattern over said fifth film, (l) dry etching said fifth film in the presence of said photoresist film pattern, thereby forming an inorganic film-pattern of said fifth film, (m) removing said photoresist film pattern by ashing, and (n) dry etching said fourth film in the presence of said inorganic film pattern, thereby patterning said fourth film.
Claim 7
Dependent Claim
45 words
A manufacturing method of a semiconductor integrated circuit according to claim 5 , wherein said fourth film is formed of a lower layer made of ruthenium and an upper layer made of titanium nitride and said fifth film is formed of a silicon oxide film.
References Cited (Backward Citations)
US5543644A
Cited
US5401680A
Cited
US5352622A
Cited
US5236550A
Cited
US5313089A
Cited
US5405796A
Cited
US5254217A
Cited
US5350705A
Cited
US5488011A
Cited
JPH08153707A
Cited
US5824563A
Cited
JPH09266200A
Cited
JPH1098162A
Cited
US5780338A
Cited
US6218231B1
Cited
US6238932B1
Cited
US5998258A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-03 | 2005-06-04 | 2005-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-03 | 2009-06-04 | 2009-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-03 | 2013-06-04 | 2013-12-04 | $7700.00 | Window Closed / Lapsed |