PCB adapter for IC chip failure analysis

Claim 2

A chip failure analysis assembly for mounting and performing failure analysis of an integrated circuit die having a plurality of leads, said failure analysis assembly comprising: a printed circuit board; a location or position on top of said printed circuit board for mounting said semiconductor die that is to be analyzed, a die that is to be analyzed being mounted on the surface of a printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die that is to be analyzed being mounted on a glass surface where the glass surface is inserted in a cut out provided in the printed circuit board; a clamping arrangement for said printed circuit board; an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus; a means for distributing electrical signals from said clamping arrangement to said location of said die to be examined; contact points between said clamping arrangement and said means for distributing electrical signals; and a means for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed, said means comprising jumper wires.

Claim 3

The failure analysis assembly of claim 1 , said clamping arrangement comprising a wire assembly of a plurality of electrical wires for connecting said electrical stimuli or stimuli response apparatus with said contact points.

Claim 4

The failure analysis assembly of claim 2 , said electrical wire assembly providing power to said contact points for biasing said die during said analysis.

Claim 5

The failure analysis assembly of claim 2 , said electrical wire assembly providing electrical stimulus signals to said contact points for functionally activating said die during said analysis.

Claim 6

The failure analysis assembly of claim 2 , said electrical wire assembly providing electrical stimulus response wiring from said contact points to said electrical interface for functionally analyzing electrical response signals during said analysis of said die.

Claim 7

The failure analysis assembly of claim 2 , said electrical wire assembly providing a multiplicity of power, electrical stimuli and electrical stimuli response wires to the device to be analyzed for biasing and analyzing said die during said analysis.

Claim 8

The failure analysis assembly of claim 1 , said contact points comprising a multiplicity of electrical contacting pads.

Claim 9

The failure analysis assembly of claim 1 , said means for distributing electrical signals from said clamping arrangement to said location for mounting said die to be analyzed comprising a multiplicity of printed circuit board wires.

Claim 10

The failure analysis assembly of claim 8 , said printed circuit board wires having electrical power or direct current supply carrying characteristics.

Claim 11

The failure analysis assembly of claim 8 , said printed circuit board wires having electrical stimulus/response signal or high frequency electrical signal carrying characteristics.

Claim 12

The failure analysis assembly of claim 8 , said printed circuit board wires having a multiplicity of power or direct current supply and electrical stimulus/response or high frequency carrying characteristics.

Claim 13

The failure analysis assembly of claim 1 , said jumper wires having power or direct current carrying characteristics.

Claim 14

The failure analysis assembly of claim 1 , said jumper wires having alternating current or high frequency carrying characteristics.

Claim 15

A chip failure analysis assembly for mounting and performing failure analysis of an integrated circuit die having a plurality of leads, said failure analysis assembly comprising: a printed circuit board; a location or position on top of said printed circuit board for mounting the semiconductor die that is to be analyzed; an opening within said circuit board which is aligned with and directly below said location or position on top of said printed circuit board for mounting the semiconductor die to be analyzed for back side analysis of said die, a die that is to be analyzed being mounted on a surface of the printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die that is to be analyzed being mounted on a glass surface where the glass surface is inserted in the opening provided in the printed circuit board; a clamping arrangement for said printed circuit board; an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus; a means for distributing electrical signals from said clamping arrangement to the die to be analyzed; contact points between said clamping arrangement and said means for distributing electrical signals; and a means for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed, said means comprising jumper wires.

Claim 16

A chip failure analysis assembly for mounting and performing failure analysis of an integrated circuit die having a plurality of leads, said failure analysis assembly comprising: a printed circuit board; a location or position on top of said printed circuit board for mounting the semiconductor die that is to be analyzed; an opening within said circuit board which is aligned with and directly below said location or position on top of said printed circuit board for mounting the semiconductor die to be analyzed for back side analysis of said die, a die that is to be analyzed being mounted on a surface of the printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die that is to be analyzed being mounted on a glass surface where the glass surface is inserted in the opening provided in the printed circuit board; a clamping arrangement for said printed circuit board; an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus; a means for distributing electrical signals from said clamping arrangement to the die to be analyzed; contact points between said clamping arrangement and said means for distributing electrical signals; and a means for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed, said means comprising jumper wires.

Claim 17

The failure analysis assembly of claim 14 , said clamping arrangement comprising a wire assembly of a plurality of electrical wires for establishing electrical analysis conditions for said die to be analyzed.

Claim 18

The failure analysis assembly of claim 15 , said electrical wire assembly providing power to said contact points for biasing said die during said analysis.

Claim 19

The failure analysis assembly of claim 15 , said electrical wire assembly providing electrical stimulus signals to said contact points for functionally activating said die during said analysis.

Claim 20

The failure analysis assembly of claim 15 , said electrical wire assembly providing electrical stimulus response wiring from said contact points to said electrical interface for functionally analyzing electrical response signals during said analysis of said die.

Claim 21

The failure analysis assembly of claim 15 , said electrical wire assembly providing a multiplicity of power, electrical stimuli and electrical stimuli response wires for the device to be analyzed for biasing and analyzing said die during said analysis.

Claim 22

The failure analysis assembly of claim 14 , said contact points comprising a multiplicity of pads.

Claim 23

The failure analysis assembly of claim 14 , said means for establishing electrical contact between said contact points and said location for mounting the die to be analyzed comprising a multiplicity of printed board wires.

Claim 24

The failure analysis assembly of claim 21 , said multiplicity of printed board wires having electrical power or direct current supply carrying characteristics.

Claim 25

The failure analysis assembly of claim 21 , said multiplicity of printed board wires having power or electrical stimulus/response signal or high frequency electrical signal carrying characteristics.

Claim 26

The failure analysis assembly of claim 21 , said multiplicity of printed board wires having a multiplicity of power or direct current supply and electrical stimulus/response or high frequency carrying characteristics.

Claim 27

The failure analysis assembly of claim 14 , said jumper wires having power or direct current carrying characteristics.

Claim 28

The failure analysis assembly of claim 14 , said jumper wires having alternating current or high frequency carrying characteristics.

Claim 31

The method of claim 27 , said clamping arrangement comprising a wire assembly of a plurality of electrical wires for connecting said electrical stimuli or stimuli response apparatus with said contact points.

Claim 32

The method of claim 28 , said electrical wire assembly providing power to said contact points for biasing said die during said analysis.

Claim 33

The method of claim 28 , said electrical wire assembly providing electrical stimulus signals to said contact points for functionally activating said die during said analysis.

Claim 34

The method of claim 28 , said electrical wire assembly providing electrical stimulus response wiring from said contact points to said electrical interface for functionally analyzing electrical response signals during said analysis of said die.

Claim 35

The method of claim 28 , said electrical wire assembly providing a multiplicity of power, electrical stimuli and electrical stimuli response wires to the device to be analyzed for biasing and analyzing said die during said analysis.

Claim 36

The method of claim 27 , said contact points comprising a multiplicity of electrical contacting pads.

Claim 37

The method of claim 27 , said means for distributing electrical signals from said clamping arrangement to said location for mounting said die to be analyzed comprising a multiplicity of printed circuit board wires.

Claim 38

The method of claim 34 , said printed circuit board wires comprising electrical power or direct current supply carrying characteristics.

Claim 39

The method of claim 34 , said printed circuit board wires comprising electrical stimulus/response signal or high frequency electrical signal carrying characteristics.

Claim 40

The method of claim 34 , said printed circuit board wires comprising a multiplicity of power or direct current supply and electrical stimulus/response or high frequency carrying characteristics.

Claim 41

The method of claim 27 , said jumper wires having power or direct current carrying characteristics.

Claim 42

The method of claim 38 , said jumper wires having alternating current or high frequency carrying characteristics.