Patent US6320453B1 successfully refreshed from Google Patents.
US6320453B1
Expired / Lapsed
US
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Method and circuit for lowering standby current in an integrated circuit
Assignee: Micron Technology Inc
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Filing: 1999-07-22
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Granted: 2001-11-20
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Expires: 2019-07-22
Abstract
Abstract An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output, and an external terminal adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate. The at least one transistor has a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
Inventors
- 👤 H. Montgomery Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:00
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
134 words
A method for reducing power consumption in an integrated circuit having a semiconductor substrate in which at least one transistor is formed, the method comprising the steps of: applying a first back-bias voltage to the semiconductor substrate from an internal source, each of the transistors on the semiconductor substrate having an associated first threshold voltage when the first back-bias voltage is applied to the substrate; selectively applying an externally generated second back-bias voltage to the substrate, the externally generated second back-bias voltage having a magnitude and polarity that increases the associated threshold voltages of the transistors on the semiconductor substrate and detecting application of the second back-bias voltage and terminating the application of the first back-bias voltage to the semiconductor substrate responsive to the externally generated second back-bias voltage being applied to the substrate.
Claim 2
Independent Claim
134 words
A method for reducing power consumption in an integrated circuit having a semiconductor substrate in which at least one transistor is formed, the method comprising the steps of: applying a first back-bias voltage to the semiconductor substrate from an internal source, each of the transistors on the semiconductor substrate having an associated first threshold voltage when the first back-bias voltage is applied to the substrate; selectively applying an externally generated second back-bias voltage to the substrate, the externally generated second back-bias voltage having a magnitude and polarity that increases the associated threshold voltages of the transistors on the semiconductor substrate and detecting application of the second back-bias voltage and terminating the application of the first back-bias voltage to the semiconductor substrate responsive to the externally generated second back-bias voltage being applied to the substrate.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein the integrated circuit comprises a memory device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-19 | 2005-05-21 | 2005-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-19 | 2009-05-21 | 2009-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-19 | 2013-05-21 | 2013-11-20 | $7700.00 | Window Closed / Lapsed |