Patent US6320238B1 successfully refreshed from Google Patents.
US6320238B1
Expired / Lapsed
US
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Gate structure for integrated circuit fabrication
Assignee: Bell Semiconductor LLC
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Filing: 1999-06-25
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Granted: 2001-11-20
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Expires: 2019-06-25
Abstract
Abstract The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
Inventors
- 👤 Isik C. Kizilyalli
- 👤 Yi Ma
- 👤 Sailesh Mansinh Merchant
- 👤 Pradip Kumar Roy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:33
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/68; H10D1/682; H10D1/684; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/01344; H10D64/693
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
75 words
An integrated circuit, comprising: a substrate; a dielectric material layer disposed over said substrate, said dielectric material layer having an equivalent electrical thickness of 2.2 nm or less, and said dielectric material layer including a stress free oxide layer located on said substrate, a grown oxide layer located on said stress free oxide layer and a layer of high-k dielectric material located on said grown oxide layer; and an electrode disposed over said dielectric layer.
Claim 2
Dependent Claim
75 words
An integrated circuit, comprising: a substrate; a dielectric material layer disposed over said substrate, said dielectric material layer having an equivalent electrical thickness of 2.2 nm or less, and said dielectric material layer including a stress free oxide layer located on said substrate, a grown oxide layer located on said stress free oxide layer and a layer of high-k dielectric material located on said grown oxide layer; and an electrode disposed over said dielectric layer.
Claim 3
Dependent Claim
44 words
An integrated circuit as recited in claim 1 , wherein said electrode is chosen from the group consisting of W, W x Si y , WSi x N y , TaSi x N y , MoSi x N y , Ta, Ti, and Mo.
Claim 4
Dependent Claim
35 words
An integrated circuit as recited in claim 1 , wherein said high-k dielectric layer is selected from the group consisting of Ta 2 O 5 , ZrO 2 , TiO 2 , and perovskite materials.
Claim 5
Dependent Claim
14 words
An integrated circuit as recited in claim 1 , wherein said electrode is metal.
Claim 6
Dependent Claim
23 words
An integrated circuit as recited in claim 1 , wherein said grown oxide layer has a thickness on the order of 0.3-0.5 nm.
Claim 7
Dependent Claim
17 words
An integrated circuit as recited in claim 1 , wherein said high-k dielectric material is substantially non-crystalline.
Claim 8
Dependent Claim
18 words
An integrated circuit as recited in claim 1 , wherein said high-k dielectric material is doped with nitrogen.
Claim 9
Dependent Claim
14 words
An integrated circuit as recited in claim 1 , wherein said substrate is silicon.
Claim 10
Dependent Claim
15 words
An integrated circuit as recited in claim 1 , wherein said substrate is epitaxial silicon.
Claim 11
Dependent Claim
28 words
An integrated circuit as recited in claim 1 , wherein said dielectric material layer has an equivalent electrical thickness in a range of approximately 1.0 to 2.2 nm.
Claim 12
Dependent Claim
55 words
An integrated circuit, comprising: a substrate; a stress free oxide layer located over said substrate; a grown oxide layer located on said stress free oxide layer; at least one layer of high-k dielectric material disposed on said grown oxide layer; and an electrode disposed directly on said at least one layer of high-k dielectric material.
Claim 13
Dependent Claim
55 words
An integrated circuit, comprising: a substrate; a stress free oxide layer located over said substrate; a grown oxide layer located on said stress free oxide layer; at least one layer of high-k dielectric material disposed on said grown oxide layer; and an electrode disposed directly on said at least one layer of high-k dielectric material.
Claim 14
Dependent Claim
31 words
An integrated circuit as recited in claim 11 , wherein said at least one layer of high-k dielectric material is tantalum pentoxide, having a thickness in the range of 3.0-15.0 nm.
Claim 15
Dependent Claim
14 words
An integrated circuit as recited in claim 11 , wherein said electrode is metal.
Claim 16
Dependent Claim
16 words
An integrated circuit as recited in claim 11 , wherein said substrate is and oxidizable layer.
Claim 17
Dependent Claim
23 words
An integrated circuit as recited in claim 11 , wherein dielectric material layer has an equivalent electrical thickness of 2.2 nm or less.
Claim 18
Dependent Claim
44 words
An integrated circuit as recited in claim 11 , wherein said electrode is chosen from the group consisting of W, W x Si y , WSi x N y , TaSi x N y , MoSi x N y , Ta, Ti, and Mo.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-19 | 2005-05-21 | 2005-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-19 | 2009-05-21 | 2009-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-19 | 2013-05-21 | 2013-11-20 | $7700.00 | Window Closed / Lapsed |