US6317819B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction
Assignee: Cufer Asset Ltd LLC
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Filing: 1999-02-24
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Granted: 2001-11-13
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Expires: 2019-02-24
Abstract
Abstract A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (7) and an internal data bus coupling together a first parallel port (3A), a second parallel port (3B), a third parallel port (3C), an external memory interface (2), and a data input/output of the first cache and the second cache.
Inventors
- 👤 Steven G. Morton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:27
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/40; G06F8/41; G06F8/45; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30072; G06F9/30098; G06F9/30101; G06F9/3012; G06F9/30123; G06F9/30127; G06F9/30138; G06F9/30141; G06F9/38; G06F9/3885; G06F9/3887
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
83 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a cache memory via a crossbar switch, and further comprising circuitry, operable during a single cycle, for performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is on other than an N-byte boundary in said cache memory, where N>1.
Claim 2
Dependent Claim
83 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a cache memory via a crossbar switch, and further comprising circuitry, operable during a single cycle, for performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is on other than an N-byte boundary in said cache memory, where N>1.
Claim 3
Dependent Claim
90 words
A digital data processor integrated circuit as in claim 1 , wherein an operation of each of said plurality of first processor elements and an operation of said second processor element are locked together during an execution of a single instruction, the single instruction specifying in a first portion thereof, that is coupled in common to each of said plurality of first processor elements, the operation of each of said plurality of first processor elements in parallel, and in a second portion thereof the operation of said second processor element.
Claim 4
Dependent Claim
32 words
A digital data processor integrated circuit as in claim 1 , and further comprising a motion estimator having inputs coupled to an output of each of said plurality of first processor elements.
Claim 5
Dependent Claim
48 words
A digital data processor integrated circuit as in claim 1 , and further comprising an internal data bus coupling together a first parallel port, a second parallel port, a third parallel port, an external memory interface, and a data input/output of said first cache and said second cache.
Claim 6
Dependent Claim
111 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a first cache via a crossbar switch, and said second processor element is coupled to a second cache; further comprising a motion estimator having inputs coupled to an output of each of said plurality of first processor elements, wherein said motion estimator operates in cooperation with said plurality of first processor elements to determine a best pixel distance value by executing a series of pixel distance calculations that are accumulated, and by a comparison for the best result.
Claim 7
Dependent Claim
111 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a first cache via a crossbar switch, and said second processor element is coupled to a second cache; further comprising a motion estimator having inputs coupled to an output of each of said plurality of first processor elements, wherein said motion estimator operates in cooperation with said plurality of first processor elements to determine a best pixel distance value by executing a series of pixel distance calculations that are accumulated, and by a comparison for the best result.
Claim 8
Dependent Claim
112 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a cache memory via a data reordering logic block, and further comprising circuitry, operable during a single cycle, for performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored on other than an N-byte boundary in said cache memory, where N>1.
Claim 9
Dependent Claim
112 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a cache memory via a data reordering logic block, and further comprising circuitry, operable during a single cycle, for performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored on other than an N-byte boundary in said cache memory, where N>1.
Claim 10
Dependent Claim
114 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a cache memory via a data reordering logic block, and further comprising circuitry, operable during a single cycle, for performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored in an interleaved manner in non-contiguous storage locations in said cache memory, where N>1.
Claim 11
Dependent Claim
114 words
A digital data processor integrated circuit comprising: a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to a cache memory via a data reordering logic block, and further comprising circuitry, operable during a single cycle, for performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored in an interleaved manner in non-contiguous storage locations in said cache memory, where N>1.
Claim 12
Dependent Claim
102 words
A digital data processor integrated circuit, comprising; a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to said second processor element; further comprising a third processor element having inputs coupled to an output of each of said plurality of first processor elements, wherein said third processor element operates in cooperation with said plurality of first processor elements to compute a value based on outputs of each of said plurality of first processor elements, wherein said third processor element is comprised of a motion estimation processor element.
Claim 13
Dependent Claim
102 words
A digital data processor integrated circuit, comprising; a plurality of functionally identical first processor elements; and a second processor element; wherein said plurality of functionally identical first processor elements are bidirectionally coupled to said second processor element; further comprising a third processor element having inputs coupled to an output of each of said plurality of first processor elements, wherein said third processor element operates in cooperation with said plurality of first processor elements to compute a value based on outputs of each of said plurality of first processor elements, wherein said third processor element is comprised of a motion estimation processor element.
Claim 14
Independent Claim
114 words
A method for operating a digital data processor, comprising: providing the digital data processor to include a plurality of functionally identical first processor elements and a second processor element; bidirectionally coupling said plurality of fictionally identical first processor elements to a cache memory via a data reordering logic block; and during a single cycle, performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored on other than an N-byte boundary in said cache memory, where N>1.
Claim 15
Independent Claim
114 words
A method for operating a digital data processor, comprising: providing the digital data processor to include a plurality of functionally identical first processor elements and a second processor element; bidirectionally coupling said plurality of fictionally identical first processor elements to a cache memory via a data reordering logic block; and during a single cycle, performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored on other than an N-byte boundary in said cache memory, where N>1.
Claim 16
Independent Claim
116 words
A method for operating a digital data processor, comprising: providing the digital data processor to include a plurality of functionally identical first processor elements and a second processor element; bidirectionally coupling said plurality of functionally identical first processor elements to a cache memory via a data reordering logic block; and during a single cycle, performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored in an interleaved manner in non-contiguous storage locations in said cache memory, where N>1.
Claim 17
Independent Claim
116 words
A method for operating a digital data processor, comprising: providing the digital data processor to include a plurality of functionally identical first processor elements and a second processor element; bidirectionally coupling said plurality of functionally identical first processor elements to a cache memory via a data reordering logic block; and during a single cycle, performing an N-byte operand cache memory read access or an N-byte operand cache memory write access, where the N-byte operand is comprised of a plurality of discrete values operated on in parallel by said plurality of functionally identical first processor elements, and where the N-byte operand is stored in an interleaved manner in non-contiguous storage locations in said cache memory, where N>1.
Claim 18
Independent Claim
94 words
A method for operating a digital data processor, comprising: providing the digital data processor to include a plurality of functionally identical first processor elements and a second processor element; further providing a third processor element having inputs coupled to an output of each of said plurality of first processor elements; and operating said third processor element in cooperation the said plurality of first processor elements to compute a value based on outputs of each of said plurality of first processor elements, wherein said third processor element is comprised of a motion estimation processor element.
Claim 19
Independent Claim
94 words
A method for operating a digital data processor, comprising: providing the digital data processor to include a plurality of functionally identical first processor elements and a second processor element; further providing a third processor element having inputs coupled to an output of each of said plurality of first processor elements; and operating said third processor element in cooperation the said plurality of first processor elements to compute a value based on outputs of each of said plurality of first processor elements, wherein said third processor element is comprised of a motion estimation processor element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-12 | 2005-05-14 | 2005-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-12 | 2009-05-14 | 2009-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-12 | 2013-05-14 | 2013-11-13 | $7700.00 | Window Closed / Lapsed |