US6313537B1
Expired / Lapsed
US
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Semiconductor device having multi-layered pad and a manufacturing method thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-11-09
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Granted: 2001-11-06
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Expires: 2018-11-09
Abstract
Abstract Provided is a semiconductor device having a multi-layered pad, including a first interlevel insulating layer formed on a semiconductor substrate; a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region; a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad; a first conductive plug formed in the first via hole; a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug; a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad; a second conductive plug formed in the second via hole; and a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug. The semiconductor device further comprises a fourth interlevel insulating layer formed on the third interlevel insulating layer having a third via hole exposing a defined region of the third conductive pad and a fourth conductive pad formed on a defined region of the fourth interlevel insulating layer, the fourth conductive pad being electrically coupled to the third conductive pad. The semiconductor device even further comprises a plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region. The plurality of buffer layers is arranged either in a mosaic layout or in a zigzag manner.
Inventors
- 👤 Sueng-Rok Lee
- 👤 Myung-Sung Kim
- 👤 Yunhee Lee
- 👤 Manjun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:13
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10W; H10W72/00; H10W72/01; H10W72/019; H10W72/20; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/9232; H10W72/931; H10W72/934; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
238 words
A semiconductor device having a multi-layered pad, comprising: a first interlevel insulating layer formed on a semiconductor substrate; a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region; a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad; a first conductive plug formed in the first via hole; a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug; a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad; a second conductive plug formed in the second via hole; a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug; and a plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region at substantially the same time as the first or second conductive pads, the plurality of buffer layers being a same material as the first or second conductive pads.
Claim 2
Dependent Claim
238 words
A semiconductor device having a multi-layered pad, comprising: a first interlevel insulating layer formed on a semiconductor substrate; a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region; a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad; a first conductive plug formed in the first via hole; a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug; a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad; a second conductive plug formed in the second via hole; a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug; and a plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region at substantially the same time as the first or second conductive pads, the plurality of buffer layers being a same material as the first or second conductive pads.
Claim 3
Dependent Claim
19 words
The semiconductor device according to claim 1 wherein the plurality of buffer layers are arranged in a mosaic layout.
Claim 4
Dependent Claim
38 words
The semiconductor device according to claim 1 wherein a distance between two adjacent buffer layers is between about 0.7 to 0.8 μm and wherein each of the plurality of buffer layers is about 0.4 to 0.6 μm wide.
Claim 5
Dependent Claim
37 words
The semiconductor device according to claim 1 wherein the plurality of buffer layers are formed of a buffer layer material different from an insulating layer material used to form the first, second, and third interlevel insulating layers.
Claim 6
Dependent Claim
22 words
The semiconductor device according to claim 4 wherein the plurality of buffer layers and the first or second conductive pads are aluminum.
Claim 7
Dependent Claim
24 words
The semiconductor device according to claim 4 wherein the plurality of buffer layers and the first or second conductive pads are a copper alloy.
Claim 8
Dependent Claim
22 words
The semiconductor device according to claim 4 wherein the plurality of buffer layers and the first or second conductive pads are polysilicon.
Claim 9
Dependent Claim
234 words
A semiconductor device having a multi-layered pad, comprising: a first interlevel insulating layer formed on a semiconductor substrate; a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region; a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad; a first conductive plug formed in the first via hole; a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug, the first and second conductive pads being arranged in a bar form; a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad; a second conductive plug formed in the second via hole; a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug; and a plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region at substantially the same time as the first or second conductive pads.
Claim 10
Dependent Claim
234 words
A semiconductor device having a multi-layered pad, comprising: a first interlevel insulating layer formed on a semiconductor substrate; a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region; a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad; a first conductive plug formed in the first via hole; a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug, the first and second conductive pads being arranged in a bar form; a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad; a second conductive plug formed in the second via hole; a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug; and a plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region at substantially the same time as the first or second conductive pads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-05 | 2005-05-07 | 2005-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-05 | 2009-05-07 | 2009-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-05 | 2013-05-07 | 2013-11-06 | $7700.00 | Window Closed / Lapsed |