Abstract A semiconductor device that meets the demand for realizing semiconductor chips in small sizes. A semiconductor device in which connection lands 20 formed on the electrode terminal carrying surface of a semiconductor chip 10 are electrically connected, through connection bumps 14 , to connection pads 22 formed on one surface of an interposing substrate 12 of an insulating material so as to face the connection lands 20 , wherein conductor wiring patterns 24 inclusive of the connection pads 22 are formed on one surface of the interposing substrate 12 , conductor wiring patterns 30 inclusive of terminal lands on where the external connection terminals 26 will be mounted, are formed on the other surface of the interposing substrate 12 , and the conductor wiring patterns 24 formed on one surface of the interposing substrate 12 are connected to the conductor wiring patterns 30 formed on the other surface of the interposing substrate 12 through vias 32 formed by filling recesses with a metal by plating, the recesses being formed to penetrate through the insulating material of the interposing substrate 12 and permitting the back surfaces of the conductor wiring patterns 24 on the side of the insulating material to be exposed on the bottom surfaces thereof.
A semiconductor device comprising: a semiconductor chip having an electrode terminal carrying surface on which electrode terminals and conductor lands electrically connected to the electrode terminals are formed; an interposing substrate of an insulating material having a front surface and a back surface and disposed with the front surface facing the electrode terminal carrying surface of the semiconductor chip, in which a conductor wiring pattern, including conductor pads, is formed on the front surface, a conductor wiring pattern, including conductor lands having a larger surface area than said conductor pads, is formed on the back surface, external connection terminals are formed on the conductor lands on the back surface, and conductor vias formed by electrolytic plating to fill viaholes with an alloy having a melting point of no more than 300° Celsius, extending through the interposing substrate electrically connecting the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface, at least one of the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface being adhered to the interposing substrate by a thermoplastic adhesive agent layer; and bumps electrically connecting the conductor lands of the semiconductor chip to the conductor pads of the interposing substrate.
Claim 2
Dependent Claim
208 words
A semiconductor device comprising: a semiconductor chip having an electrode terminal carrying surface on which electrode terminals and conductor lands electrically connected to the electrode terminals are formed; an interposing substrate of an insulating material having a front surface and a back surface and disposed with the front surface facing the electrode terminal carrying surface of the semiconductor chip, in which a conductor wiring pattern, including conductor pads, is formed on the front surface, a conductor wiring pattern, including conductor lands having a larger surface area than said conductor pads, is formed on the back surface, external connection terminals are formed on the conductor lands on the back surface, and conductor vias formed by electrolytic plating to fill viaholes with an alloy having a melting point of no more than 300° Celsius, extending through the interposing substrate electrically connecting the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface, at least one of the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface being adhered to the interposing substrate by a thermoplastic adhesive agent layer; and bumps electrically connecting the conductor lands of the semiconductor chip to the conductor pads of the interposing substrate.
Claim 3
Dependent Claim
18 words
A semiconductor device according to claim 1 , wherein the conductor pads are formed on the conductor vias.