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EP0918354A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Wafer-scale assembly of chip-size packages

Assignee: Texas Instruments Inc
•
Filing: 1998-11-20
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Granted: —
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Expires: 2018-11-20
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Abstract

Abstract A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors. After cooling, the solder balls solidify and the first polymer film is removed. The process is repeated for assembling sequentially a wafer-scale patterned interposer overlying all of the solder balls and the wafer and contacting each solder ball with a soldered joint, and a second wafer-scale patterned film carrying solder balls contacting the interposer. In each process, the wafer is heated uniformly and rapidly and without moving it, the alignment is maintained during heating by mechanically compensating for the thermal stretching of the polymer film, and the uniformity of the height of the liquid solder balls is controlled by mechanical stoppers or position closed-loop linear actuators. The second film is removed after cooling. Other embodiments are also disclosed.

Inventors

  • 👤 Katherine E Heinen
  • 👤 Darvin R Edwards
  • 👤 Elizabeth E. Jacobs

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-04 08:21
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0446; H10P72/0444; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W90/00; H10W90/701; H10W70/65; H10W70/654; H10W70/656; H10W72/00; H10W72/01; H10W72/013; H10W72/01331; H10W72/071; H10W72/072; H10W72/07251; H10W72/20

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 153 words
A semiconductor assembly comprising: a semiconductor wafer having a plurality of integrated circuits, each circuit having a plurality of metal contact pads as electrical entry and exit ports; an electrically conductive array, substantially parallel to the surface of said wafer, comprising a multitude of coupling members positioned so that at least one of said coupling members is electrically in contact with one circuit contact pad, respectively, while remaining insulated from its adjacent coupling member; an interposer of electrically insulating material having electrically conductive paths extending through said interposer from one surface to the opposite surface, forming electrical entry and exit ports on said insulating interposer; said interposer positioned substantially parallel to the wafer surface and having one of its surfaces attached to said planar array, thereby electrically connecting said ports to at least some of said coupling members; and a planar array of solder balls attached to said exit ports of said interposer.
Claim 2
Dependent Claim 36 words
The semiconductor assembly of Claim 1 wherein said coupling members comprise a multitude of electrically conductive fibers extending through an electrically nonconductive layer from one surface to the opposite surface, while remaining insulated from adjacent fibers.
Claim 3
Dependent Claim 17 words
The semiconductor assembly of Claim 1 or Claim 2 wherein said electrically insulating interposer is mechanically elastic.
Claim 4
Dependent Claim 18 words
The semiconductor assembly of Claim 3 wherein said mechanically elastic interposer comprises polyimide, epoxy, resin, and/or reinforcing material.
Claim 5
Dependent Claim 17 words
The semiconductor assembly of Claim 1 or Claim 2 wherein said electrically insulating interposer comprises ceramic material.
Claim 6
Dependent Claim 39 words
The semiconductor assembly of any of Claims 1 to 5 wherein said electrically conductive paths comprise gold or copper when said electrically insulating interposer is organic material, and comprise tungsten or tungsten alloy when said insulating interposer is ceramic.
Claim 7
Dependent Claim 35 words
The semiconductor assembly of any of Claims 1 to 6 wherein said electrical entry and exit ports of said electrically insulating interposer comprise copper or tungsten arrays overlaid by palladium, gold, platinum, or platinum-rich alloy.
Claim 8
Independent Claim 186 words
A method for the fabrication of a semiconductor assembly comprising: providing a semiconductor wafer having a plurality of integrated circuits, each circuit having a plarality of metal contact pads as electrical entry and exit ports; forming a planar array of solder balls attached to said contact pads of said semiconductor wafer so that each of said contact pads is contacted by one of said solder balls; providing an interposer of electrically insulating material having electrically conductive paths from one surface to the opposite surface, forming electrical entry and exit ports on said insulating interposer; aligning said- interposer with said solder balls so that each port is placed into alignment with one of said solder balls on said semiconductor wafer; contacting said ports and said solder balls; applying energy to said semiconductor wafer such that said wafer increases uniformly in temperature and transfers heat to said solder balls, causing the solder balls to reach a liquid state; removing said energy such that said solder balls cool and harden, forming physical bonds between said solder balls and said ports; and separating the resulting composite structure into discrete chips.
Claim 9
Independent Claim 218 words
A method for the fabrication of a semiconductor assembly comprising: providing a semiconductor wafer having a plurality of integrated circuits, each circuit having a plurality of metal contact pads as electrical entry and exit ports; forming a first planar array of solder balls attached to said contact pads of said semiconductor wafer so that each of said contact pads is contacted by one of said solder balls; providing an interposer of electrically insulating material having electrically conductive paths from one surface to the opposite surface, forming electrical entry and exit ports on said insulating interposer; aligning said interposer with said solder balls so that each port is placed into alignment with one of said solder balls on said semiconductor wafer; contacting said ports and said solder balls; applying energy to said semiconductor wafer such that said wafer increases uniformly in temperature and transfers heat to said solder balls, causing said solder balls to reach a liquid state; removing said energy such that said solder balls cool and harden, forming physical bonds between said solder balls and said ports; forming a second planar array of solder balls attached to said exit ports of said interposer so that each of said exit ports is contacted by one of said solder balls; and separating the resulting composite structure into discrete chips.
Claim 10
Independent Claim 245 words
A method for the fabrication of a semiconductor assembly comprising: providing a semiconductor wafer having a plurality of integrated circuits, each circuit having a plurality of metal contact pads as electrical entry and exit ports; providing an adhesive layer having a multitude of electrically conductive fibers extending through electrically nonconductive material from one surface to the opposite surface of the layer while remaining insulated from adjacent fibers; providing an interposer of electrically insulating material having electrically conductive paths from one surface to the opposite surface, forming electrical entry and exit ports on said insulating interposer; placing said interposer vertically and in contact with said adhesive substrate; providing a polymer film having a plurality of discrete adhesive areas; providing a plurality of solder balls, one of said solder balls being placed on each of said adhesive areas; aligning said polymer film to said interposer so that each of said solder balls is placed into alignment with one of said ports; placing said solder balls in contact with said ports; applying energy to said semiconductor wafer such that said wafer uniformly increases in temperature and transfer heat to said adhesive substrate, said interposer and said solder balls, causing said solder balls to reach a liquid state; removing said energy such that all said contacts form physical bonds and said solder balls cool and harden, forming physical bonds between said solder balls and said ports; removing said polymer film; and separating the resulting composite structure into discrete chips.

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