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US6297086B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Application of excimer laser anneal to DRAM processing

Assignee: International Business Machines Corp
•
Filing: 1999-03-11
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Granted: 2001-10-02
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Expires: 2019-03-11
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Abstract

Abstract Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.

Inventors

  • 👤 Suryanarayan G. Hegde
  • 👤 Kam Leung Lee
  • 👤 Jack A. Mandelman
  • 👤 Carl J. Radens

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 05:15
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0385

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 186 words
A process of fabricating a trench capacitor semiconductor memory structure comprising the steps of: (a) providing an intermediate trench capacitor structure comprising a trench storage capacitor formed within a semiconductor substrate or wafer and a patterned gate region formed on said substrate or wafer, wherein said trench storage capacitor comprises at least a lower region having a temperature sensitive material situated between a bottom electrode and a top electrode and a doped polysilicon region formed on said top electrode; (b) forming source/drain regions in said semiconductor substrate or wafer in areas adjacent to said patterned gate region; (c) annealing the structure of step (b) using an excimer laser under conditions effective to activate the source/drain regions without substantially degrading the temperature sensitive material in said lower region of said storage capacitor and to cause substantial outdiffusion of dopant from said doped polysilicon region thereby forming a strap outdiffusion region in said substrate adjacent to said trench storage capacitor; (d) forming an insulating layer over said structure of step (c); (e) planarizing said insulating layer; and (f) forming borderless diffusion contacts on said semiconductor substrate or wafer.
Claim 2
Dependent Claim 186 words
A process of fabricating a trench capacitor semiconductor memory structure comprising the steps of: (a) providing an intermediate trench capacitor structure comprising a trench storage capacitor formed within a semiconductor substrate or wafer and a patterned gate region formed on said substrate or wafer, wherein said trench storage capacitor comprises at least a lower region having a temperature sensitive material situated between a bottom electrode and a top electrode and a doped polysilicon region formed on said top electrode; (b) forming source/drain regions in said semiconductor substrate or wafer in areas adjacent to said patterned gate region; (c) annealing the structure of step (b) using an excimer laser under conditions effective to activate the source/drain regions without substantially degrading the temperature sensitive material in said lower region of said storage capacitor and to cause substantial outdiffusion of dopant from said doped polysilicon region thereby forming a strap outdiffusion region in said substrate adjacent to said trench storage capacitor; (d) forming an insulating layer over said structure of step (c); (e) planarizing said insulating layer; and (f) forming borderless diffusion contacts on said semiconductor substrate or wafer.
Claim 3
Dependent Claim 38 words
The process of claim 1 wherein said temperature sensitive material is a material which may become unstable and also oxidize silicon when exposed to temperatures over 550° C. and has a dielectric constant of about 7 or higher.
Claim 4
Dependent Claim 21 words
The process of claim 2 wherein said temperature sensitive material has a dielectric constant of from about 20 to about 10,000.
Claim 5
Dependent Claim 39 words
The process of claim 1 wherein said temperature sensitive material is a material selected from the group consisting of barium strontium titanium oxide (BSTO), lead zirconium titanium oxide (PZTO), strontium bismuth tantalate (SBT) and Ta 2 O 5 .
Claim 6
Dependent Claim 12 words
The process of claim 4 wherein said temperature sensitive material is BSTO.
Claim 7
Dependent Claim 27 words
The process of claim 1 wherein said temperature sensitive material is formed by a deposition process selected from the group consisting of chemical vapor deposition and sputtering.
Claim 8
Dependent Claim 23 words
The process of claim 1 wherein said excimer laser is a 308 nm laser, a 193 nm laser or a 248 nm laser.
Claim 9
Dependent Claim 38 words
The process of claim 7 wherein said 308 nm excimer laser anneal step is operated at a fluence of from about 500 to about 1100 mJ/cm 2 and a pulse duration of about 25 to about 100 ns.
Claim 10
Dependent Claim 38 words
The process of claim 8 wherein said 308 nm excimer laser anneal step is operated at a fluence of from about 700 to about 1000 mJ/cm 2 and a pulse duration of about 30 to about 60 ns.
Claim 11
Dependent Claim 21 words
The process of claim 1 wherein said excimer laser anneal step is carried out using a single pulse or multiple pulses.
Claim 12
Dependent Claim 17 words
The process of claim 1 wherein said excimer laser anneal step is repeating any number of times.
Claim 13
Dependent Claim 34 words
The process of claim 1 wherein said semiconductor substrate or wafer is composed of a semiconductor material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP and all other III/V compounds.
Claim 14
Dependent Claim 15 words
The process of claim 12 wherein said semiconductor substrate or wafer is composed of Si.
Claim 15
Dependent Claim 25 words
The process of claim 1 wherein said semiconductor substrate or wafer contains at least one shallow trench isolation region abutting said trench storage capacitor region.
Claim 16
Dependent Claim 23 words
The process of claim 14 wherein said shallow trench isolation region includes a thermal silicon dioxide layer and a shallow trench isolation dielectric.
Claim 17
Dependent Claim 33 words
The process of claim 1 wherein said patterned gate region comprises a layer of polysilicon, another layer of polysilicon, a salicide layer and a cap layer, said layers formed on a gate oxide.
Claim 18
Dependent Claim 39 words
The process of claim 1 wherein said bottom and top electrodes are formed of the same or different conducting material selected from the group consisting of RuO 2 , SrRuO 3 , La—Sr—Co—O, IrO 2 , Pt and Ir.
Claim 19
Dependent Claim 34 words
The process of claim 1 wherein said bottom and top electrodes are formed by a deposition process selected from the group consisting of chemical vapor deposition, metallo-organic chemical vapor deposition, electroplating and electrodeless plating.
Claim 20
Dependent Claim 20 words
The process of claim 1 wherein said pattern gate region further includes oxide spacers formed on the exterior sidewalls thereof.
Claim 21
Dependent Claim 36 words
The process of claim 1 wherein said excimer laser anneal step provides limited heating of said semiconductor substrate or wafer which is within 0.4 μm or less from the surface of said semiconductor substrate or wafer.

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3.5 Years (Year 4) 2004-10-01 2005-04-02 2005-10-02 $2000.00 Window Closed / Lapsed
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