Process for forming a high density semiconductor device

Claim 2

A semiconductor device comprising: a) a semiconductor substrate having at least one patterned gate conductor and at least one patterned cap insulator formed on said gate conductor having edges thereon; b) a dielectric masking layer formed over said at least one cap insulator; c) at least one opening formed in said dielectric masking layer; d) said at least one opening in said dielectric masking layer comprising a mask, aligned with at least one opening in said substrate for a capacitor; and e) a trench formed in said substrate self-aligned with one of said edges.

Claim 3

The semiconductor device of claim 1 wherein: said patterned cap insulator comprises silicon nitride.

Claim 4

A semiconductor device comprising: a) a substrate having at least two patterned gate conductors thereon, each gate conductor overlying a gate insulator; b) at least one insulating region formed over and on said sides of each of said at least two patterned gate conductors; c) at least one trench capacitor formed in said substrate, such that a sidewall of said trench capacitor is self-aligned with an edge of an insulating region on said side of a said gate conductor; d) a doped conductive region extending under said gate insulator and electrically contacting a buried strap electrode formed on the surface of said trench capacitor, and e) said trench capacitor being formed with a central electrode and a dielectric collar below said buried strap electrode, said collar surrounding the upper end of said central electrode of said capacitor.

Claim 5

A semiconductor device comprising: a) a substrate having at least two patterned gate conductors thereon, each gate conductor overlying a gate insulator; b) at least one insulating region formed over and on said sides of each of said at least two patterned gate conductors; c) at least one trench capacitor formed in said substrate, such that a sidewall of said trench capacitor is self-aligned with an edge of an insulating region on said side of a said gate conductor; d) a doped conductive region extending under said gate insulator and electrically contacting a buried strap electrode formed on the surface of said trench capacitor, and e) said trench capacitor being formed with a central electrode and a dielectric collar below said buried strap electrode, said collar surrounding the upper end of said central electrode of said capacitor.

Claim 6

The semiconductor device of claim 3 wherein: said capacitor comprises a thin nitride layer formed on said sidewalls of said trench, and said trench being filled with a first, heavily doped amorphous, polysilicon layer within said thin nitride layer, said first, heavily doped, amorphous, polysilicon layer being deeply recessed below said top of said trench, said collar formed on said sidewalls of said trench above said deeply recessed first, heavily doped, amorphous, olsilicon layer being formed of a dielectric oxide, a second, heavily doped, amorphous polysilicon layer, said second, heavily doped, amorphous, polysillicon layer being shallowly recessed below said top of said trench, leaving a shallow recess above said second, heavily doped polysilicon layer, and said buried strap electrode being composed of doped, intrinsic polysilicon filling said shallow recess in contact with a junction of an array transistor next to said trench.

Claim 7

The semiconductor device of claim 4 wherein: said patterned gate conductor further has a sidewall insulator.

Claim 8

The semiconductor device of claim 4 wherein: said dielectric masking layer comprises a layer of material selected from the group consisting of silicon nitride and TEOS.

Claim 9

The semiconductor device of claim 4 further characterized by the absence of a surface strap conductor in a plurality of array transistors.

Claim 10

The semiconductor device of claim 4 wherein: said thin nitride material comprises a lining material having a high dielectric constant and a thickness of about 4 nm.

Claim 11

The semiconductor device of claim 3 wherein: said trench capacitor includes a lining material having a high dielectric constant and said lining material is selected from the group consisting of silicon nitride, silicon oxide, Ta 2 O 5 , and Ba x Sr.sub.(1-x) TiO 3 (BSTO).

Claim 12

The semiconductor device of claim 3 wherein: said trench capacitor includes a lining material having a high dielectric constant.

Claim 13

The semiconductor device of claim 3 wherein: said trench capacitor is formed in a trench having a depth of abou t 4 micrometers to about 5 micrometers in said substrate, an oxide collar formed on said sidewalls of said trench above said deeply recessed first, heavily doped silicon layer recessed to a depth of about 100 nm below said substrate surface, said trench being filled with a heavily doped polysilicon layer, said first heavily doped amorphous polysilicon layer being recessed to a substantial depth of about 1.3 micrometers below said top of said trench, a second, heavily arsenic doped silicon layer, formed inside said collar and above said heavily doped silicon layer, said second polysilicon layer being shallowly recessed to about 50 nm in said trench leaving a shallow recess above said second, heavily doped, amorphous polysilicon layer and said collar, a buried strap of doped, intrinsic polysilicon filling said shallow recess in contact with said junction of an array transistor next to said trench.

Claim 14

A semiconductor device comprising: a semiconductor device substrate having at least one patterned gate conductor thereon with source/drain regions with an insulating region formed over and on sides of said gate conductor, said insulating region having sides with edges; a deep trench formed in said substrate for a storage capacitance for a memory cell self-aligned with one of said edges of said insulating region, a dielectric lining layer (40) formed on the walls of said trench and a dielectric collar (44) formed at the top of said trench to provide vertical isolation of said memory cell, said collar and said lining layer being recessed below the top of said trench, leaving a portion of a recess space on the top of said trench, a doped polysilicon capacitor plate filling the space inside of said collar and said dielectric lining layer, and recessed below the top of said trench leaving the balance of said recess space on the top of said trench, a strap conductor formed in said trench on the surface of said collar, said lining layer and said doped polysilicon capacitor plate.

Claim 15

A semiconductor device comprising: a semiconductor device substrate having at least one patterned gate conductor thereon with source/drain regions with an insulating region formed over and on sides of said gate conductor, said insulating region having sides with edges; a deep trench formed in said substrate for a storage capacitance for a memory cell self-aligned with one of said edges of said insulating region, a dielectric lining layer (40) formed on the walls of said trench and a dielectric collar (44) formed at the top of said trench to provide vertical isolation of said memory cell, said collar and said lining layer being recessed below the top of said trench, leaving a portion of a recess space on the top of said trench, a doped polysilicon capacitor plate filling the space inside of said collar and said dielectric lining layer, and recessed below the top of said trench leaving the balance of said recess space on the top of said trench, a strap conductor formed in said trench on the surface of said collar, said lining layer and said doped polysilicon capacitor plate.

Claim 16

The semiconductor device of claim 12 wherein: said lining layer comprises a material having a high dielectric constant.

Claim 17

The semiconductor device of claim 13 wherein: said trench capacitor is formed in a trench having a depth of from about 4 micrometers to about 5 micrometers in said substrate, said capacitor comprises a thin nitride layer formed on said sidewalls of said trench, and said trench being filled with a first, heavily doped silicon layer, said first, heavily doped silicon layer being recessed to about 1.3 micrometers below said top of said trench, an oxide collar formed on said sidewalls of said trench above said deeply recessed first, heavily doped silicon layer, a second, heavily doped silicon layer, said second, heavily doped silicon layer being shallowly recessed to about 150 nm below said top of said trench, leaving a shallow recess above said second, heavily doped silicon layer, said second, heavily doped silicon layer having a top surface, a buried strap of doped, intrinsic polysilicon formed on said top surface of said second, heavily doped silicon layer filling said shallow recess in contact with said junction of an array transistor next to said trench.

Claim 18

A semiconductor device comprising: a substrate having at least two patterned gate conductors thereon, said gate conductors having sides, each gate conductor overlying a gate insulator; at least one insulating region formed over and on said sides of each of said at least two patterned gate conductors; at least one trench capacitor formed in a lined trench having a depth of from about 4 micrometers to about 5 micrometers in said substrate, such that each sidewall of said trench capacitor is self-aligned with an edge of an insulating region on one of said sides of a said gate conductor; a doped conductive region extending under said gate insulator and electrically contacting an electrode of said trench capacitor, said capacitor comprises a thin reoxidized, nitride layer formed lining said lined trench, with said lined trench being filled with a first, heavily doped, amorphous, polysilicon layer, said first, heavily doped, amorphous, polysilicon layer being deeply recessed to about 1.3 micrometers below said top of said lined trench, an oxide collar formed on said sidewalls of said trench above said deeply recessed first, heavily doped, amorphous, polysilicon layer about 30 nm thick, a second, heavily doped, amorphous, polysilicon layer, said seond, heavily doped, amorphous, polysilicon layer being shallowly recessed to about 150 nm below said top of said trench, leaving a shallow recess above said second, he avily doped silicon layer, a buried strap of doped, intrinsic polysilicon filling said shallow recess in contact with said junction of an array transistor next to said trench, and said buried strap being recessed to about 50 nm below said top of said trench, and a TEOS oxide film formed and planarized over said trench.

Claim 19

A semiconductor device comprising: a substrate having at least two patterned gate conductors thereon, said gate conductors having sides, each gate conductor overlying a gate insulator; at least one insulating region formed over and on said sides of each of said at least two patterned gate conductors; at least one trench capacitor formed in a lined trench having a depth of from about 4 micrometers to about 5 micrometers in said substrate, such that each sidewall of said trench capacitor is self-aligned with an edge of an insulating region on one of said sides of a said gate conductor; a doped conductive region extending under said gate insulator and electrically contacting an electrode of said trench capacitor, said capacitor comprises a thin reoxidized, nitride layer formed lining said lined trench, with said lined trench being filled with a first, heavily doped, amorphous, polysilicon layer, said first, heavily doped, amorphous, polysilicon layer being deeply recessed to about 1.3 micrometers below said top of said lined trench, an oxide collar formed on said sidewalls of said trench above said deeply recessed first, heavily doped, amorphous, polysilicon layer about 30 nm thick, a second, heavily doped, amorphous, polysilicon layer, said seond, heavily doped, amorphous, polysilicon layer being shallowly recessed to about 150 nm below said top of said trench, leaving a shallow recess above said second, he avily doped silicon layer, a buried strap of doped, intrinsic polysilicon filling said shallow recess in contact with said junction of an array transistor next to said trench, and said buried strap being recessed to about 50 nm below said top of said trench, and a TEOS oxide film formed and planarized over said trench.

Claim 20

The semiconductor device of claim 15 wherein: a lining layer comprising a material having a high dielectric constant is formed on the walls of said trench.