Method of forming a high density self-aligned stack in trench

Claim 1

A method for fabricating a DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements, comprising the steps of: providing a silicon substrate having field oxide isolation regions which isolate said field effect transistor; forming a first insulating layer over said field effect transistor and said field oxide isolation regions; patterning said first insulating layer to create an exposed region of said silicon substrate between said gate electrode and said field oxide isolation region; etching said exposed region to form a first trench in said silicon substrate; forming a second insulating layer over said field effect transistor, said field oxide isolation region and in said first trench; removing said second insulating layer from a portion of the bottom of said first trench to expose said silicon substrate; then thermally oxidizing said silicon substrate at bottom of said first trench to form an insulating layer mask; removing remainder of said second insulating layer from said first trench, said field effect transistor and said field oxide isolation region; etching in a vertical direction that portion of said silicon substrate in said first trench that is not masked by said insulating layer mask, whereby a pillar is formed under said insulating layer mask in the center of a final trench; removing said insulating layer mask; forming a diffusion layer in said final trench and over said pillar, and over said field effect transistor and said field oxide isolation region, wherein said diffusion layer has been doped with a conductivity-imparting dopant; heating said DRAM cell to cause outdiffusion of said conductivity-imparting dopant into surfaces of said final trench and said pillar, whereby a capacitor signal node is formed in contact with source region of said field effect transistor; removing said diffusion layer; forming a capacitor dielectric in said final trench and over said pillar; and forming a capacitor ground plate over said capacitor dielectric.

Claim 2

A method for fabricating a DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements, comprising the steps of: providing a silicon substrate having field oxide isolation regions which isolate said field effect transistor; forming a first insulating layer over said field effect transistor and said field oxide isolation regions; patterning said first insulating layer to create an exposed region of said silicon substrate between said gate electrode and said field oxide isolation region; etching said exposed region to form a first trench in said silicon substrate; forming a second insulating layer over said field effect transistor, said field oxide isolation region and in said first trench; removing said second insulating layer from a portion of the bottom of said first trench to expose said silicon substrate; then thermally oxidizing said silicon substrate at bottom of said first trench to form an insulating layer mask; removing remainder of said second insulating layer from said first trench, said field effect transistor and said field oxide isolation region; etching in a vertical direction that portion of said silicon substrate in said first trench that is not masked by said insulating layer mask, whereby a pillar is formed under said insulating layer mask in the center of a final trench; removing said insulating layer mask; forming a diffusion layer in said final trench and over said pillar, and over said field effect transistor and said field oxide isolation region, wherein said diffusion layer has been doped with a conductivity-imparting dopant; heating said DRAM cell to cause outdiffusion of said conductivity-imparting dopant into surfaces of said final trench and said pillar, whereby a capacitor signal node is formed in contact with source region of said field effect transistor; removing said diffusion layer; forming a capacitor dielectric in said final trench and over said pillar; and forming a capacitor ground plate over said capacitor dielectric.

Claim 12

A method for fabricating a DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements, comprising the steps of: providing a silicon substrate having field oxide isolation regions which isolate said field effect transistor; forming a first insulating layer over said field effect transistor and said field oxide isolation regions; patterning said first insulating layer to create an exposed region of said silicon substrate between said gate electrode and said field oxide isolation region; etching said exposed region to form a first trench in said silicon substrate; forming a second insulating layer over said field effect transistor, said field oxide isolation region and in said first trench; removing said second insulating layer from a portion of the bottom of said first trench to expose said silicon substrate; then thermally oxidizing said silicon substrate at bottom of said first trench to form an insulating layer mask; removing remainder of said second insulating layer from said first trench, said field effect transistor and said field oxide isolation region; etching in a vertical direction that portion of said silicon substrate in said first trench that is not masked by said insulating layer mask, whereby a pillar is formed under said insulating layer mask in the center of a final trench; removing said insulating layer mask; forming a first conducting layer in said final trench and over said pillar, and over said field effect transistor and said field oxide isolation region, wherein said first conducting layer is doped with a conductivity-imparting dopant; forming a third insulating layer over said first conducting layer; patterning said first conducting layer and said third insulating layer, to form a capacitor signal node and capacitor dielectric, respectively, in said final trench and over said pillar, whereby said capacitor signal node is formed in contact with source region of said field effect transistor; and forming a capacitor ground plate over said capacitor dielectric.

Claim 13

A method for fabricating a DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements, comprising the steps of: providing a silicon substrate having field oxide isolation regions which isolate said field effect transistor; forming a first insulating layer over said field effect transistor and said field oxide isolation regions; patterning said first insulating layer to create an exposed region of said silicon substrate between said gate electrode and said field oxide isolation region; etching said exposed region to form a first trench in said silicon substrate; forming a second insulating layer over said field effect transistor, said field oxide isolation region and in said first trench; removing said second insulating layer from a portion of the bottom of said first trench to expose said silicon substrate; then thermally oxidizing said silicon substrate at bottom of said first trench to form an insulating layer mask; removing remainder of said second insulating layer from said first trench, said field effect transistor and said field oxide isolation region; etching in a vertical direction that portion of said silicon substrate in said first trench that is not masked by said insulating layer mask, whereby a pillar is formed under said insulating layer mask in the center of a final trench; removing said insulating layer mask; forming a first conducting layer in said final trench and over said pillar, and over said field effect transistor and said field oxide isolation region, wherein said first conducting layer is doped with a conductivity-imparting dopant; forming a third insulating layer over said first conducting layer; patterning said first conducting layer and said third insulating layer, to form a capacitor signal node and capacitor dielectric, respectively, in said final trench and over said pillar, whereby said capacitor signal node is formed in contact with source region of said field effect transistor; and forming a capacitor ground plate over said capacitor dielectric.

Claim 23

A method for fabricating a DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements, comprising the steps of: providing a silicon substrate having field oxide isolation regions which isolate said field effect transistor; forming a first insulating layer over said field effect transistor and said field oxide isolation regions; patterning said first insulating layer to create an exposed region of said silicon substrate between said gate electrode and said field oxide isolation region; etching said exposed region to form a first trench in said silicon substrate; forming a second insulating layer over said field effect transistor, said field oxide isolation region and in said first trench; removing said second insulating layer from a portion of the bottom of said first trench to expose said silicon substrate; then thermally oxidizing said silicon substrate at bottom of said first trench to form an insulating layer mask; removing remainder of said second insulating layer from said first trench, said field effect transistor and said field oxide isolation region; etching in a vertical direction that portion of said silicon substrate in said first trench that is not masked by said insulating layer mask, whereby a pillar is formed under said insulating layer mask in the center of a final trench; removing said insulating layer mask; forming a conductive layer along the surfaces of said final trench and said pillar, adjacent to said source region of said field effect transistor, whereby said conductive layer is a capacitor signal node; forming a capacitor dielectric over said conductive layer; and forming a capacitor ground plate over said capacitor dielectric.

Claim 24

A method for fabricating a DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements, comprising the steps of: providing a silicon substrate having field oxide isolation regions which isolate said field effect transistor; forming a first insulating layer over said field effect transistor and said field oxide isolation regions; patterning said first insulating layer to create an exposed region of said silicon substrate between said gate electrode and said field oxide isolation region; etching said exposed region to form a first trench in said silicon substrate; forming a second insulating layer over said field effect transistor, said field oxide isolation region and in said first trench; removing said second insulating layer from a portion of the bottom of said first trench to expose said silicon substrate; then thermally oxidizing said silicon substrate at bottom of said first trench to form an insulating layer mask; removing remainder of said second insulating layer from said first trench, said field effect transistor and said field oxide isolation region; etching in a vertical direction that portion of said silicon substrate in said first trench that is not masked by said insulating layer mask, whereby a pillar is formed under said insulating layer mask in the center of a final trench; removing said insulating layer mask; forming a conductive layer along the surfaces of said final trench and said pillar, adjacent to said source region of said field effect transistor, whereby said conductive layer is a capacitor signal node; forming a capacitor dielectric over said conductive layer; and forming a capacitor ground plate over said capacitor dielectric.