Chemical mechanical polishing of FeRAM capacitors

Claim 3

A method according to claim 1, wherein the capacitor structure is selected from the group consisting of stack capacitors and trench capacitors.

Claim 4

A method according to claim 1, further comprising depositing a dielectric buffer layer over the capacitor precursor structure prior to planarizing same by chemical mechanical polishing.

Claim 5

A process according to claim 1, carried out without dry etchlinig of the electrode layers or dry etching of the ferroelectric layer, and wherein the ferroelectric capacitor structure has a feature size below 1 μm.

Claim 6

A process according to claim 1, wherein the ferroelectric capacitor structure has a feature size below 0.35 μm.

Claim 7

A process for fabricating a stack capacitor on a substrate including buried circuitry overlaid by an isolation dielectric material, comprising: forming a first via in the isolation dielectric material to the buried circuitry in the substrate; depositing a plug in the first via; planarizitig the isolation dielectric material and plug; depositing the isolation dielectric material over the planarized plug; forming a capacitor recess in a surface of the isolation dielectric material; depositing over the isolation dielectric material in sequence, a bottom electrode layer, a ferroelectric layer and a top electrode layer, optionally with deposition of a layer of a conductive barrier material between the isolation dielectric material and the bottom electrode layer, and optionally with deposition of a dielectric buffer layer over the top electrode layer, to form a film stack of the sequentially deposited layers; planarizing the film stack by chemical mechanical polishing to yield three-dimensional stack capacitor in the capacitor recess; sequentially depositing an inIsulating passivation layer and an inter-level dielectric layer to form a barrier structure over the three-dimenisionial stack capacitor in the capacitor recess; forming a second via in the barrier structure; depositing over the barrier structure and second via in sequence a diffusion barrier layer and a metallization layer, to conformally fill the second via in the barrier structure; and pattteriling the metallization layer to form a line structure for the three-dimensional stack capacitor.

Claim 8

A process for fabricating a stack capacitor on a substrate including buried circuitry overlaid by an isolation dielectric material, comprising: forming a first via in the isolation dielectric material to the buried circuitry in the substrate; depositing a plug in the first via; planarizitig the isolation dielectric material and plug; depositing the isolation dielectric material over the planarized plug; forming a capacitor recess in a surface of the isolation dielectric material; depositing over the isolation dielectric material in sequence, a bottom electrode layer, a ferroelectric layer and a top electrode layer, optionally with deposition of a layer of a conductive barrier material between the isolation dielectric material and the bottom electrode layer, and optionally with deposition of a dielectric buffer layer over the top electrode layer, to form a film stack of the sequentially deposited layers; planarizing the film stack by chemical mechanical polishing to yield three-dimensional stack capacitor in the capacitor recess; sequentially depositing an inIsulating passivation layer and an inter-level dielectric layer to form a barrier structure over the three-dimenisionial stack capacitor in the capacitor recess; forming a second via in the barrier structure; depositing over the barrier structure and second via in sequence a diffusion barrier layer and a metallization layer, to conformally fill the second via in the barrier structure; and pattteriling the metallization layer to form a line structure for the three-dimensional stack capacitor.

Claim 9

A process according to claim 6, wherein the substrate is formed of a material selected from the group consisting of silicon and gallium arsenide.

Claim 10

A process according to claim 6, wherein the substrate is formed of silicon.

Claim 11

A process according to claim 6, wherein the isolation dielectric material comprises a material selected from the g,roup consisting of SiO 2 , Si 3 N 4 , B-doped SiO 2 , P-doped SiO 2 , B and P-doped SiO 2 , low dielectric constant organic insulator materials, SiO x F y , B-doped SiO x F y , P-doped SiO x F y , and B and P-doped SiO x F y , wherein x+y=2.

Claim 12

A process according to claim 6, wherein the first via is are fabricated in the isolation dielectric material by photolitliography and diy etch removal of isolation dielectric material from a via area of the material.

Claim 13

A process according to claim 6, wherein the plug is formed of a material selected from the group consisting of Si doped with a dopant selected from the group consisting of B, P, As and combinations thereof, and W.

Claim 14

A process according to claim 6, wherein the substrate and plug are planarized using a planarization method selected from the group consisting of dry etching and chemical mechanical polishing.

Claim 15

A process according to claim 6, wherein the isolation dielectric material comprises a material selected from the group consisting of SiO 2 , Si 3 N 4 , B-doped SiO 2 , P-doped SiO 2 , B and P-doped SiO 2 , low dielectric constant organic insulators, SiO x F y , B-doped SiO x F y , P-doped SiO x F y , and B and P-doped SiO x F y , wherein x+y=2.

Claim 16

A process according to claim 6, wherein the isolation dielectric material is deposited over the plug by a method selected from the group consisting of CVD, sputtering and wet deposition methods.

Claim 17

A process according to claim 6, wherein the capacitor recess is formed by photolithography and dry-etching.

Claim 18

A process according to claim 6, with a conductive barrier layer between the isolation dielectric material and the bottom electrode layer, wherein a top surface of the conductive plug is cleaned by a method selected from the group consisting of sputter etching and heat treating, prior to the deposition of the conductive barrier layer.

Claim 19

A process according to claim 6, wherein the conductive barrier layer is formed of a material selected from the ,roup consisting of TaWN, TaN, TiWN, TaSiN, TaAlN, NbN, ZrN, TaTiN, TiN, TiSiN, TiAlN, IrO 2 , and SiC.

Claim 20

A process according to claim 6, wherein the bottom electrode is formed of a material selected from the group consisting of noble metals, noble metal/non-noble metal alloys, noble metal/noble metal oxide mixtures, noble metal multilayers, and noble metal/non-noble metal multilayers.

Claim 21

A process according to claim 6, wherein the top electrode is formed of a noble metal, noble metal/non-noble metal alloys, noble metal/noble metal oxide mixtures, noble metal multilayers, and noble metal/non-noble metal multilayers.

Claim 22

A process according to claim 6, wherein the ferroelectric material layer is formed of a material selected from the group consisting of PZT, SBT, bismuth titanate, BST, LaCaMnO 3 , and materials formed by covalent or non-covalent substitutions in the foregoing materials.

Claim 23

A process according to claim 6, wherein each of the top electrode layer, ferroelectric layer and bottom electrode layer deposition steps is independently carried out by a method selected from the group consisting of sputtering and chemical vapor deposition.

Claim 24

A process according to claim 6, wherein each of the top electrode layer, ferroelectric layer and bottom electrode laver deposition steps is carried out by chemical vapor deposition.

Claim 25

A process according to claim 6, wherein the film stack chemical mechanical polishing comprises mechanical polishing with a slurry including (i) an abrasive material selected from the group consisting of metal oxides, metal nitrides and metal carbides, and (ii) chemical additives for removal of the conductive barrier layer, bottom electrode layer, ferroelectric layer and top electrode layer.

Claim 26

A process according to claim 23, wherein the slurry comprises an abrasive material selected from the group consisting of silica, alumina and ceria.

Claim 27

A process according to claim 23, wherein the slurry comprises an abrasive material selected from the group consisting of metal nitrides and metal carbides.

Claim 28

A process according to claim 6, wherein the film stack chemical mechanical polishing comprises multiple chemical mechanical polishing steps, each carried out with a different slurry material.

Claim 29

A process according to claim 6, with a conductive barrier layer between the isolation dielectric material and the bottom electrode layer, wherein the conductive barrier layer comprises a polishing stop layer, and wherein the polishing stop layer is subsequently removed by a removal technique selected from the group consisting of chemical mechanical polishing and dry etching.

Claim 30

A process acccording to claim 6, further comprising after planarizing the film stack a step of removing conductive residue at edges of the three-dimensional stack capacitor by a wet or dry etch.

Claim 31

A process according to claim 6, further comprising after the film stack chemical mechanical polishing, conducting a post-chemical mechanical polishing annealing to remove physical and/or chemical damage to the ferroelectric layer during the chemical mechanical polishing.

Claim 32

A process according to claim 6, wherein the barrier structure comprising the insulating passivation layer and inter-level dielectric layer, is deposited by a method selected from the group consisting of CVD, sputtering and wet deposition methods.

Claim 33

A process according to claim 6, wherein the insulating passivation layer is formed of a material selected from the group consisting of TiO 2 , HfO 2 , Nb 2 O 5 , ZrO 2 , Ta 2 O 5 , Si 3 N 4 and mixtures.

Claim 34

A process according to claim 6, wherein the inter-level dielectric layer is formed of a material selected from the group consisting of SiO 2 , Si 3 N 4 , B-doped SiO 2 , P-doped SiO 2 , B and P-doped SiO 2 , low dielectric constant organic insulators, SiO x F y , B-doped SiO x F y , P-doped SiO x F y , and B and P-doped SiO x F y , wherein x+y=2.

Claim 35

A process according to claim 6, wherein the second via is formed in the barrier structure by photolithography and dry etching.

Claim 36

A process according to claim 6, wherein a dielectric buffer layer is deposited over the top electrode layer prior to planarizing the film stack by chemical mechanical polishing.

Claim 37

A process according to clain 6, wherein the metallization layer is formed of a material selected fiom the group consisting of W, Al, Cu, and Al--Cu alloys.

Claim 38

A process according to clain 6, wherein the metallization layer is formed of a material selected fiom the group consisting of W, Al, Cu, and Al--Cu alloys.

Claim 39

A process according to claim 6, wherein the metallization layer is patterned by photolithography and dry-etching.

Claim 40

A process according to claim 6, wherein the metallization layer is patterned by a damascene or a dual damascene process.

Claim 41

A process according to claim 6, wherein the three-dimensional stack capacitor has a feature size below 0.35 μm.

Claim 42

A process for fabricating a trench capacitor on a substrate including a device region, comprising: forming a capacitor recess in the substrate; depositing over the capacitor recess in sequence, a bottom electrode layer, a ferroelectric layer and a top electrode layer, optionally with deposition of a layer of a conductive barrier material between the capacitor recess and the bottom electrode layer, and optionally with deposition of a dielectric buffer layer over the top electrode layer, to forn a film of the sequentially deposited layers; planarizing the film of the sequentially deposited layers by chemical mechanical polishing to yield a trench capacitor in the capacitor recess; sequentially depositing an inisulating passivation layer and an inter-level dielectric layer to form a barrier structure over the trncli capacitor in the capacitor recess; forming a via in the barrier structure; depositing over the barrier structure and via a diffusion barrier layer; patterning the diffusion barrier layer in a selected pattern; forming a first via to a device region of the substrate; forming circuitry structure over the substrate including a plate and a first line element of a word and bit line structure for the trench capacitor; depositing an isolation dielectric material over the plate and line elements; forming a second via to the device region of the substrate; depositing a metallization layer, to conforinally fill the second via in the isolation dielectric material; and patterinig the metallization layer to form a complimenitary line element of the word and bit line structure for the trench capacitor.

Claim 43

A process for fabricating a trench capacitor on a substrate including a device region, comprising: forming a capacitor recess in the substrate; depositing over the capacitor recess in sequence, a bottom electrode layer, a ferroelectric layer and a top electrode layer, optionally with deposition of a layer of a conductive barrier material between the capacitor recess and the bottom electrode layer, and optionally with deposition of a dielectric buffer layer over the top electrode layer, to forn a film of the sequentially deposited layers; planarizing the film of the sequentially deposited layers by chemical mechanical polishing to yield a trench capacitor in the capacitor recess; sequentially depositing an inisulating passivation layer and an inter-level dielectric layer to form a barrier structure over the trncli capacitor in the capacitor recess; forming a via in the barrier structure; depositing over the barrier structure and via a diffusion barrier layer; patterning the diffusion barrier layer in a selected pattern; forming a first via to a device region of the substrate; forming circuitry structure over the substrate including a plate and a first line element of a word and bit line structure for the trench capacitor; depositing an isolation dielectric material over the plate and line elements; forming a second via to the device region of the substrate; depositing a metallization layer, to conforinally fill the second via in the isolation dielectric material; and patterinig the metallization layer to form a complimenitary line element of the word and bit line structure for the trench capacitor.

Claim 44

A process according to claim 39, wherein the substrate is formed of a material selected from the group consisting of silicon and gallium arsenide.

Claim 45

A process according to claim 39, wherein the substrate is formed of silicon.

Claim 46

A process according to claim 39, wherein the isolation dielectric material comprises a material selected from the group consisting of SiO 2 , Si 3 N 4 , B-doped SiO 2 , P-doped SiO 2 , B and P-doped SiO 2 , low dielectric constant organic insulator materials, SiO x F y , B-doped SiO x F y , P-doped SiO x F y , and B and P-doped SiO x F y , wherein x+y=2.

Claim 47

A process according to claim 39, wherein the second via is fabricated in the isolation dielectric insulating material by photolithography and dry etch removal of isolation dielectric insulating material from a via area of the material.

Claim 48

A process according to claim 39, wherein the capacitor recess is formed by photolithography and dry-etching.

Claim 49

A process according to claim 38, wherein the conductive barrier layer is formed of a material selected from the group consisting of TaWN, TaN, TiWN, TaSiN, TaAlN, NbN, ZrN, TaTiN, TiN, TiSiN, TiAlN, IrO 2 , and SiC.

Claim 50

A process according to claim 39, wherein the bottom electrode layer is formed of a material selected from the group consisting of noble metals, noble metal/non-noble metal alloys, noble metal/noble metal oxide mixtures, noble metal multilayers, and noble metal/non-noble metal multilayers.

Claim 51

A process according to claim 39, wherein the top electrode layer is formed of a material selected from the group consisting of noble metals, noble metal/non-noble metal alloys, noble metal/noble metal oxide mixtures, noble metal multilayers, and noble metal/non-noble metal multilayers.

Claim 52

A process according to claim 39, wherein the ferroelectric material layer is formed of a material selected from the group consisting of PZT, SBT, bismuth titanate, BST, LaCaMnO 3 , and materials formed by covalent or non-covalent substitutions in the foregoing materials.

Claim 53

A process according to claim 39, wherein each of the top electrode layer, ferroelectric layer and bottom electrode layer deposition steps is independently carried out by a method selected from the group consisting of sputtering and chemical vapor deposition.

Claim 54

A process according to claim 39, wherein each of the top electrode layer, ferroelectric layer and bottom electrode layer deposition steps is carried out by chemical vapor deposition.

Claim 55

A process according to claim 39, wherein the film chemical mechanical polishing comprises mechanical polishing with a slurry including (i) an abrasive material selected from the group consisting of metal oxides, metal nitrides and metal carbides, and (ii) chemical additives for removal of the conductive barrier layer, bottom electrode layer, ferroelectric layer and top electrode layer.

Claim 56

A process according to claim 51, wherein the slurry comprises an oxide abrasive material selected from the group consisting of silica, alumina and ceria.

Claim 57

A process according to claim 39, wherein the film chemical mechanical polishing comprises multiple chemical mechanical polishing steps, each carried out with a different slurry material.

Claim 58

A process according to claim 39, with a conductive barrier layer beneath the bottom electrode layer, wherein the conductive barrier layer comprises a polishing stop layer, and wherein the polishing stop layer is subsequently removed by a removal technique selected from the group consisting of chemical mechanical polishing and dry etching.

Claim 59

A process according to claim 39, further comprising after planarizing the film a step of removing conductive residue at edges of the trench capacitor by a wet or dry etch.

Claim 60

A process according to claim 39, wherein the barrier structure comprising the insulating passivation layer and inter-level dielectric layer, is deposited by a method selected from the group consisting of CVD, sputtering and wet deposition methods.

Claim 61

A process according to claim 39, wherein the insulating passivation layer is formed of a material selected from the group consisting of TiO 2 , HfO 2 , Nb 2 O 5 , ZrO 2 , Ta 2 O 5 , Si 3 N 4 and mixtures thereof.

Claim 62

A process according to claim 39, wherein the inter-level dielectric layer is formed of a material selected from the group consisting of SiO 2 , Si 3 N 4 , B-doped SiO 2 , P-doped SiO 2 , B and P-doped SiO 2 , low dielectric constant organic insulators, SiO x F y , B-doped SiO x F y , P-doped SiO x F y , and B and P-doped SiO x F y , wherein x+y=2.

Claim 63

A process according to claim 39, wherein the via is formed in the barrier structure by photolithography and dry-etching.

Claim 64

A process according to claim 39, wherein a dielectric buffer layer is deposited over the top electrode layer prior to planarizing the film stack by chemical mechanical polishing.

Claim 65

A process according to claim 39, wherein the metallization layer is formed of a material selected from the group consisting of W, Al, Cu, and Al--Cu alloys.

Claim 66

A process according to claim 39, wherein the metallization is patterned by photolithography and dry-etching.

Claim 67

A process according to claim 39, wherein the metallization is patterned by a damascene or a dual damascene process.

Claim 68

A process according to claim 39, wherein the substrate comprises buried circuitry.

Claim 69

A process according to claim 39, wherein the substrate comprises p-type silicon material.

Claim 70

A process according to claim 39, wherein the circuitry structure is formed at least in part by deposition of polysilicon.

Claim 71

A process according to claim 39, wherein the trench capacitor has a feature size below 0.35 μm.

Claim 72

A process according to claim 6, further comprising depositing a dielectric buffer layer over the film stack prior to planarizing same by chemical mechanical polishing.

Claim 73

A process according to claim 39, further comprising depositing a dielectric buffer layer over the film of the sequentially deposited layers prior to planarizing same by chemical mechanical polishing.