Stacked container capacitor using chemical mechanical polishing

Claim 1

A method for forming a stacked container capacitor for use within an integrated circuit comprising: forming upon a semiconductor substrate a first dielectric layer having a first isotropic etch rate in an isotropic etch process; forming upon the first dielectric layer a second dielectric layer, the second dielectric layer having a second isotropic etch rate in the isotropic etch process, the second isotropic etch rate being greater than the first isotropic etch rate; forming a patterned mask layer upon the second dielectric layer; anisotropically etching through the patterned mask layer an anisotropically etched aperture at least partially through the first dielectric layer, the anisotropic etching being accomplished with an anisotropic etch process; isotropically etching through the patterned mask layer the second dielectric layer to yield an isotropically etched aperture, the isotropically etched aperture having a ledge formed above the first dielectric layer and below the patterned masking layer, the anisotropic etching and the isotropic etching together yielding a completely etched aperture; removing then the patterned masking layer; forming then into the completely etched aperture a first polysilicon layer, the first polysilicon layer not completely filling the completely etched aperture; forming upon the first polysilicon layer a third dielectric layer, the third dielectric layer not completely filling the completely etched aperture; forming upon the third dielectric layer a second polysilicon layer; and planarizing then the completely etched aperture until there is revealed a flange formed from the first polysilicon layer where the first polysilicon layer is formed into the ledge.

Claim 2

A method for forming a stacked container capacitor for use within an integrated circuit comprising: forming upon a semiconductor substrate a first dielectric layer having a first isotropic etch rate in an isotropic etch process; forming upon the first dielectric layer a second dielectric layer, the second dielectric layer having a second isotropic etch rate in the isotropic etch process, the second isotropic etch rate being greater than the first isotropic etch rate; forming a patterned mask layer upon the second dielectric layer; anisotropically etching through the patterned mask layer an anisotropically etched aperture at least partially through the first dielectric layer, the anisotropic etching being accomplished with an anisotropic etch process; isotropically etching through the patterned mask layer the second dielectric layer to yield an isotropically etched aperture, the isotropically etched aperture having a ledge formed above the first dielectric layer and below the patterned masking layer, the anisotropic etching and the isotropic etching together yielding a completely etched aperture; removing then the patterned masking layer; forming then into the completely etched aperture a first polysilicon layer, the first polysilicon layer not completely filling the completely etched aperture; forming upon the first polysilicon layer a third dielectric layer, the third dielectric layer not completely filling the completely etched aperture; forming upon the third dielectric layer a second polysilicon layer; and planarizing then the completely etched aperture until there is revealed a flange formed from the first polysilicon layer where the first polysilicon layer is formed into the ledge.

Claim 18

A method for forming a stacked container capacitor within an integrated circuit memory cell comprising: forming upon a semiconductor substrate a field effect transistor structure comprising a gate oxide, a gate electrode and at least one source/drain electrode; forming upon the semiconductor substrate a first dielectric layer having a first isotropic etch rate in an isotropic etch process; forming upon the first dielectric layer a second dielectric layer, the second dielectric layer having a second isotropic etch rate in the isotropic etch process, the second isotropic etch rate being greater than the first isotropic etch rate; forming a patterned mask layer upon the second dielectric layer, a pattern of the patterned mask layer corresponding to location of the source/drain electrode; anisotropically etching through the pattern of the patterned mask layer an aperture completely through the first dielectric layer to reach the surface of the source/drain electrode, the anisotropic etching being accomplished with an anisotropic etch process; isotropically etching through the patterned mask layer the second dielectric layer to yield an isotropically etched aperture, the isotropically etched aperture having a ledge formed above the first dielectric layer and below the patterned masking layer, the anisotropic etching and the isotropic etching together yielding a completely etched aperture; removing then the patterned masking layer; forming then into the completely etched aperture a first polysilicon layer, the first polysilicon layer not completely filling the completely etched aperture; forming upon the first polysilicon layer a third dielectric layer, the third dielectric layer not completely filling the completely etched aperture; forming upon the third dielectric layer a second polysilicon layer; and planarizing then the completely etched aperture until there is revealed a flange formed from the first polysilicon layer where the first polysilicon layer is formed into the ledge.

Claim 19

A method for forming a stacked container capacitor within an integrated circuit memory cell comprising: forming upon a semiconductor substrate a field effect transistor structure comprising a gate oxide, a gate electrode and at least one source/drain electrode; forming upon the semiconductor substrate a first dielectric layer having a first isotropic etch rate in an isotropic etch process; forming upon the first dielectric layer a second dielectric layer, the second dielectric layer having a second isotropic etch rate in the isotropic etch process, the second isotropic etch rate being greater than the first isotropic etch rate; forming a patterned mask layer upon the second dielectric layer, a pattern of the patterned mask layer corresponding to location of the source/drain electrode; anisotropically etching through the pattern of the patterned mask layer an aperture completely through the first dielectric layer to reach the surface of the source/drain electrode, the anisotropic etching being accomplished with an anisotropic etch process; isotropically etching through the patterned mask layer the second dielectric layer to yield an isotropically etched aperture, the isotropically etched aperture having a ledge formed above the first dielectric layer and below the patterned masking layer, the anisotropic etching and the isotropic etching together yielding a completely etched aperture; removing then the patterned masking layer; forming then into the completely etched aperture a first polysilicon layer, the first polysilicon layer not completely filling the completely etched aperture; forming upon the first polysilicon layer a third dielectric layer, the third dielectric layer not completely filling the completely etched aperture; forming upon the third dielectric layer a second polysilicon layer; and planarizing then the completely etched aperture until there is revealed a flange formed from the first polysilicon layer where the first polysilicon layer is formed into the ledge.