Method of fabricating a semiconductor device having shallow junctions in source-drain regions and a gate electrode with a low resistance silicide layer

Claim 1

A method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate having element isolating regions in the substrate, and ion-implanting channel stop layers underlying said element isolating regions; forming a gate oxide film at a location for a gate between the element isolating regions on a surface of the substrate, forming an ion-implanted threshold voltage regulating layer under the gate oxide film in the substrate, coating the gate oxide film with a gate polycrystalline layer, forming a silicide layer on the gate polycrystalline layer, and etching the gate oxide film, the gate polycrystalline layer, and the silicide layer to form a gate electrode region, said silicide layer having a resistance; prior to formation of source and drain regions, subjecting the semiconductor substrate to an annealing process with an annealing temperature greater than 850° C. comprising one of a furnace annealing process or a rapid thermal annealing process for activating the ion implanted channel stop layers, the ion implanted threshold voltage regulating layer, and the gate polycrystalline layer, and for reducing said resistance of said silicide layer; in an ion implanting process, implanting ions into the semiconductor substrate to provide shallow junction source and drain regions having a depth not greater than 100 nm, said source and drain regions flanking the gate electrode region; and subjecting the source and drain regions to an activating annealing process for activating the ions implanted in the source and drain regions, said activating annealing process comprising irradiating the substrate with a pulse laser beam which results in the activating of the implanted ions in the source and drain regions without deepening the shallow junction source and drain regions since said pulse laser beam influences only a surface layer in the semiconductor substrate having a thickness no greater than 100 nm.

Claim 2

A method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate having element isolating regions in the substrate, and ion-implanting channel stop layers underlying said element isolating regions; forming a gate oxide film at a location for a gate between the element isolating regions on a surface of the substrate, forming an ion-implanted threshold voltage regulating layer under the gate oxide film in the substrate, coating the gate oxide film with a gate polycrystalline layer, forming a silicide layer on the gate polycrystalline layer, and etching the gate oxide film, the gate polycrystalline layer, and the silicide layer to form a gate electrode region, said silicide layer having a resistance; prior to formation of source and drain regions, subjecting the semiconductor substrate to an annealing process with an annealing temperature greater than 850° C. comprising one of a furnace annealing process or a rapid thermal annealing process for activating the ion implanted channel stop layers, the ion implanted threshold voltage regulating layer, and the gate polycrystalline layer, and for reducing said resistance of said silicide layer; in an ion implanting process, implanting ions into the semiconductor substrate to provide shallow junction source and drain regions having a depth not greater than 100 nm, said source and drain regions flanking the gate electrode region; and subjecting the source and drain regions to an activating annealing process for activating the ions implanted in the source and drain regions, said activating annealing process comprising irradiating the substrate with a pulse laser beam which results in the activating of the implanted ions in the source and drain regions without deepening the shallow junction source and drain regions since said pulse laser beam influences only a surface layer in the semiconductor substrate having a thickness no greater than 100 nm.

Claim 3

A method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate having element isolating regions in the substrate, and ion-implanting channel stop layers underlying said element isolating regions; forming a gate oxide film at a location for a gate between the element isolating regions on a surface of the substrate, forming an ion-implanted threshold voltage regulating layer under the gate oxide film in the substrate, coating the gate oxide film with a gate polycrystalline layer, forming a silicide layer on the gate polycrystalline layer, and etching the gate oxide film, the gate polycrystalline layer, and the silicide layer to form a gate electrode region, said silicide layer having a resistance; prior to formation of source and drain regions, subjecting the semiconductor substrate to an annealing process with an annealing temperature greater than 850° C. comprising one of a furnace annealing process or a rapid thermal annealing process for activating the ion implanted channel stop layers, the ion implanted threshold voltage regulating layer, and the gate polycrystalline layer, and for reducing said resistance of said silicide layer; forming an LDD structure in the substrate flanking the gate electrode region at both sides by subjecting the substrate to a first ion implanting process and then subjecting the substrate to a first activating annealing process in which the semiconductor substrate is irradiated to activate ions implanted in the substrate in the first ion implanting process; in a second ion implanting process, implanting ions into the semiconductor substrate to provide shallow junction source and drain regions formed by the ions implanted in the second implantation process having a depth not greater than 100 nm, said source and drain regions flanking the gate electrode region; and subjecting the source and drain regions to a second activating annealing process for activating the ions implanted in the second ion implantation process in the source and drain regions, said second activating annealing process comprising irradiating the substrate with a pulse laser beam which results in the activating of the ions implanted in the second ion implantation process in the source and drain regions without deepening the shallow junction source and drain regions since said pulse laser beam influences only a surface layer in the semiconductor substrate having a thickness no greater than 100 nm.

Claim 4

A method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate having element isolating regions in the substrate, and ion-implanting channel stop layers underlying said element isolating regions; forming a gate oxide film at a location for a gate between the element isolating regions on a surface of the substrate, forming an ion-implanted threshold voltage regulating layer under the gate oxide film in the substrate, coating the gate oxide film with a gate polycrystalline layer, forming a silicide layer on the gate polycrystalline layer, and etching the gate oxide film, the gate polycrystalline layer, and the silicide layer to form a gate electrode region, said silicide layer having a resistance; prior to formation of source and drain regions, subjecting the semiconductor substrate to an annealing process with an annealing temperature greater than 850° C. comprising one of a furnace annealing process or a rapid thermal annealing process for activating the ion implanted channel stop layers, the ion implanted threshold voltage regulating layer, and the gate polycrystalline layer, and for reducing said resistance of said silicide layer; forming an LDD structure in the substrate flanking the gate electrode region at both sides by subjecting the substrate to a first ion implanting process and then subjecting the substrate to a first activating annealing process in which the semiconductor substrate is irradiated to activate ions implanted in the substrate in the first ion implanting process; in a second ion implanting process, implanting ions into the semiconductor substrate to provide shallow junction source and drain regions formed by the ions implanted in the second implantation process having a depth not greater than 100 nm, said source and drain regions flanking the gate electrode region; and subjecting the source and drain regions to a second activating annealing process for activating the ions implanted in the second ion implantation process in the source and drain regions, said second activating annealing process comprising irradiating the substrate with a pulse laser beam which results in the activating of the ions implanted in the second ion implantation process in the source and drain regions without deepening the shallow junction source and drain regions since said pulse laser beam influences only a surface layer in the semiconductor substrate having a thickness no greater than 100 nm.