US6277682B1
Expired / Lapsed
US
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Source drain implant process for mixed voltage CMOS devices
Assignee: Texas Instruments Inc
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Filing: 1999-08-25
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Granted: 2001-08-21
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Expires: 2019-08-25
Abstract
Abstract A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device 24 and a high voltage device 26 comprising the steps of obtaining active regions in a substrate 10 with gates 30 and 32 for the low voltage device 24 and the high voltage device 26 , respectively, obtaining lightly implanted source and drain extensions 38 and 40 for the low voltage device 24 , forming a side wall 42, 44, 46 and 48 next to each gate 30 and 32 , and angularly implanting each of the source and drain regions 52, 54, 56 and 58 with an impurity 50 of a selected type for both the low voltage device 24 and the high voltage device 26 , to eliminate the need for separately implanting the first voltage device and second voltage device with different source-drain extensions. The method of the present invention tailors the source-drain implant conditions (energy, dose, angle 60 , and thermal drive) to create the source-drain profiles of a reliable high voltage device 26 without degrading the performance of the low voltage device 24.
Inventors
- 👤 George R. Misium
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:33
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
147 words
A method for manufacturing a mixed voltage CMOS integrated circuit comprising the steps of: (a) forming a first gate oxide and a second gate oxide on the substrate; (b) forming a first gate on the first gate oxide and a second gate on the second gate oxide; (c) lightly implanting the substrate with dopants of a first conductivity type, wherein a first photoresist layer is patterned to mask the second gate, the source and drain regions associated with the second gate, and the regions associated with transistors having channels of a second conductivity type; (d) forming side wall dielectrics next to the first gate and next to the second gate; (e) heavily implanting the substrate at an acute angle with dopants of the first conductivity type, wherein a second photoresist layer is patterned to mask the regions associated with transistors having channels of the second conductivity type.
Claim 2
Independent Claim
147 words
A method for manufacturing a mixed voltage CMOS integrated circuit comprising the steps of: (a) forming a first gate oxide and a second gate oxide on the substrate; (b) forming a first gate on the first gate oxide and a second gate on the second gate oxide; (c) lightly implanting the substrate with dopants of a first conductivity type, wherein a first photoresist layer is patterned to mask the second gate, the source and drain regions associated with the second gate, and the regions associated with transistors having channels of a second conductivity type; (d) forming side wall dielectrics next to the first gate and next to the second gate; (e) heavily implanting the substrate at an acute angle with dopants of the first conductivity type, wherein a second photoresist layer is patterned to mask the regions associated with transistors having channels of the second conductivity type.
Claim 3
Dependent Claim
20 words
The method as recited in claim 1 , wherein the second gate oxide is thicker than the first gate oxide.
Claim 4
Dependent Claim
18 words
The method as recited in claim 1 , wherein the second gate is longer than the first gate.
Claim 5
Dependent Claim
29 words
The method as recited in claim 1 , wherein the acute angle is in the range of approximately 25 and approximately 35 from a line vertical to the substrate.
Claim 6
Dependent Claim
19 words
The method as recited in claim 1 , wherein the substrate is rotated at least once during step (e).
Claim 7
Dependent Claim
15 words
The method as recited in claim 1 , wherein the first conductivity type is N-type.
Claim 8
Dependent Claim
15 words
The method as recited in claim 1 , wherein the first conductivity type is P-type.
Claim 9
Dependent Claim
18 words
The method as recited in claim 1 , further comprising the step of forming a side wall oxide.
Claim 10
Dependent Claim
17 words
The method as recited in claim 1 , further comprising the step of applying a thermal drive.
Claim 11
Independent Claim
112 words
A method for manufacturing a CMOS integrated circuit with a first voltage device and a second voltage device comprising the steps of: (a) obtaining active regions in a substrate with gates for both the first voltage device and the second voltage device; (b) obtaining lightly implanted source and drain regions for the first voltage device; (c) forming a side wall dielectric next to each gate; and (d) angularly implanting each of the source and drain regions with an impurity of a selected type for both the first voltage device and the second voltage device, to eliminate the need for separately implanting the first voltage device and second voltage device with source-drain profiles.
Claim 12
Independent Claim
112 words
A method for manufacturing a CMOS integrated circuit with a first voltage device and a second voltage device comprising the steps of: (a) obtaining active regions in a substrate with gates for both the first voltage device and the second voltage device; (b) obtaining lightly implanted source and drain regions for the first voltage device; (c) forming a side wall dielectric next to each gate; and (d) angularly implanting each of the source and drain regions with an impurity of a selected type for both the first voltage device and the second voltage device, to eliminate the need for separately implanting the first voltage device and second voltage device with source-drain profiles.
Claim 13
Dependent Claim
28 words
The method as recited in claim 10 , wherein step (b) further comprises formation of lightly implanted source and drain regions for N-channel devices and P-channel devices sequentially.
Claim 14
Dependent Claim
32 words
The method as recited in claim 10 , wherein the angularly implanting is at an angle in the range of approximately 25° to approximately 35° from a line vertical to the substrate.
Claim 15
Dependent Claim
20 words
The method as recited in claim 10 , wherein the impurity of a selected type in step (d) is N-type.
Claim 16
Dependent Claim
20 words
The method as recited in claim 10 , wherein the impurity of a selected type in step (d) is P-type.
Claim 17
Dependent Claim
18 words
The method as recited in claim 10 , wherein the first voltage device is a low voltage device.
Claim 18
Dependent Claim
17 words
The method as recited in claim 10 , wherein the second voltage device lacks source-drain extension areas.
Claim 19
Dependent Claim
16 words
The method as recited in claim 10 , wherein the substrate is rotated during step (d).
Claim 20
Dependent Claim
17 words
The method as recited in claim 10 , further comprising the step of applying a thermal drive.
Claim 21
Dependent Claim
11 words
An integrated circuit produced by the method of claim 10 .
Claim 22
Dependent Claim
146 words
A low voltage and high voltage CMOS apparatus formed after performing the steps of: (a) obtaining active regions in the substrate with gate oxides of differentiated thicknesses for the low voltage devices and the high voltage devices; (b) obtaining lightly implanted source and drain regions with N-type impurities for N-channel low voltage devices; (c) obtaining lightly implanted source and drain regions with P-type impurities for P-channel low voltage devices; (d) forming side wall dielectrics next to each gate with selected widths for the low voltage devices and the high voltage devices; (e) angularly implanting the source and drain regions of the N-channel low voltage devices and the N-channel high voltage devices with additional N-type impurities; (f) angularly implanting the source and drain regions of the P-channel low voltage devices and the P-channel high voltage devices with additional P-type impurities; and (g) applying an appropriate thermal drive.
Claim 23
Dependent Claim
146 words
A low voltage and high voltage CMOS apparatus formed after performing the steps of: (a) obtaining active regions in the substrate with gate oxides of differentiated thicknesses for the low voltage devices and the high voltage devices; (b) obtaining lightly implanted source and drain regions with N-type impurities for N-channel low voltage devices; (c) obtaining lightly implanted source and drain regions with P-type impurities for P-channel low voltage devices; (d) forming side wall dielectrics next to each gate with selected widths for the low voltage devices and the high voltage devices; (e) angularly implanting the source and drain regions of the N-channel low voltage devices and the N-channel high voltage devices with additional N-type impurities; (f) angularly implanting the source and drain regions of the P-channel low voltage devices and the P-channel high voltage devices with additional P-type impurities; and (g) applying an appropriate thermal drive.
Claim 24
Dependent Claim
28 words
The apparatus as recited in claim 20 , wherein the channel length of the low voltage devices is shorter than the channel length of the high voltage devices.
Claim 25
Dependent Claim
19 words
The apparatus as recited in claim 20 , wherein the high voltage devices have no source drain extension areas.
References Cited (Backward Citations)
US5047358A
Cited
US5606191A
Cited
US6020231A
Cited
US5686324A
Cited
US5827747A
Cited
US6100125A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-20 | 2005-02-19 | 2005-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-20 | 2009-02-19 | 2009-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-20 | 2013-02-19 | 2013-08-21 | $7700.00 | Window Closed / Lapsed |