High density programmable read-only memory employing double-wall spacers

Claim 1

A method of forming a contact hole on a storage cell for electrically programmable read-only memory of the type having spaced-apart gate structures, said method comprising: forming a dielectric region atop a subset of said spaced-apart gate structures, said dielectric region having two side regions; forming adjacent to said subset of spaced-apart gate structures and said dielectric region disposed thereon, a first sidewall spacer, wherein said first sidewall spacer covers at least a part of said two side regions; forming adjacent to said first sidewall spacer, a second sidewall spacer, defining spaced-apart insulated gate structures, said second sidewall spacer having a height that is generally equal to a height of said first sidewall spacer; depositing atop of said spaced-apart insulated gate structures, an intermetal dielectric layer; and forming an aperture in said intermetal dielectric layer, with said aperture being positioned so as to be in superimposition with a portion of each of said insulated gate structures including said first and second sidewall spacers, and a region of said substrate disposed therebetween.

Claim 2

A method of forming a contact hole on a storage cell for electrically programmable read-only memory of the type having spaced-apart gate structures, said method comprising: forming a dielectric region atop a subset of said spaced-apart gate structures, said dielectric region having two side regions; forming adjacent to said subset of spaced-apart gate structures and said dielectric region disposed thereon, a first sidewall spacer, wherein said first sidewall spacer covers at least a part of said two side regions; forming adjacent to said first sidewall spacer, a second sidewall spacer, defining spaced-apart insulated gate structures, said second sidewall spacer having a height that is generally equal to a height of said first sidewall spacer; depositing atop of said spaced-apart insulated gate structures, an intermetal dielectric layer; and forming an aperture in said intermetal dielectric layer, with said aperture being positioned so as to be in superimposition with a portion of each of said insulated gate structures including said first and second sidewall spacers, and a region of said substrate disposed therebetween.

Claim 10

A method of forming a contact on a storage cell for electrically programmable read-only memory of the type having a plurality of spaced-apart polysilicon gate structures, said method comprising: forming a silicon nitride region atop of a subset of said plurality of spaced-apart gate structures, said silicon nitride region having two side regions; forming adjacent to each of the gate structures of said subset said silicon nitride region disposed thereon, silicon oxide sidewall spacer, wherein said silicon oxide sidewall spacer covers at least a part of said two side regions; forming adjacent to said silicon oxide sidewall spacer, a silicon nitride sidewall spacer while leaving the silicon nitride region atop the spaced apart gate structures exposed, thereby insulating the gate structures of said subset, defining insulated gate structures; depositing atop of said insulated gate structures, an intermetal dielectric layer; forming an aperture in said intermetal dielectric layer, with said aperture being positioned so as to be in superimposition with a portion of each of said insulated gate structures including said first and second sidewall spacers, and a region of said substrate disposed therebetween; and depositing a metallic contact layer atop of said intermetal dielectric layer, said metallic contact layer including a plug portion disposed within said aperture, said metallic contact layer including said plug portion deposited in a single step.

Claim 11

A method of forming a contact on a storage cell for electrically programmable read-only memory of the type having a plurality of spaced-apart polysilicon gate structures, said method comprising: forming a silicon nitride region atop of a subset of said plurality of spaced-apart gate structures, said silicon nitride region having two side regions; forming adjacent to each of the gate structures of said subset said silicon nitride region disposed thereon, silicon oxide sidewall spacer, wherein said silicon oxide sidewall spacer covers at least a part of said two side regions; forming adjacent to said silicon oxide sidewall spacer, a silicon nitride sidewall spacer while leaving the silicon nitride region atop the spaced apart gate structures exposed, thereby insulating the gate structures of said subset, defining insulated gate structures; depositing atop of said insulated gate structures, an intermetal dielectric layer; forming an aperture in said intermetal dielectric layer, with said aperture being positioned so as to be in superimposition with a portion of each of said insulated gate structures including said first and second sidewall spacers, and a region of said substrate disposed therebetween; and depositing a metallic contact layer atop of said intermetal dielectric layer, said metallic contact layer including a plug portion disposed within said aperture, said metallic contact layer including said plug portion deposited in a single step.

Claim 16

A method for applying self-align contact technology to an electrically programmable read-only memory device, said method comprising: receiving a semiconductor substrate having said electrically programmable read-only device thereon, wherein said electrically programmable read-only memory device includes a plurality of spaced-apart gate structures and first spacers adjoined at the side of a subset of said plurality of spaced-apart gate structures; depositing a dielectric layer above said semiconductor substrate, said dielectric layer having two side regions, wherein said first spacers cover at least a part of said two side regions; applying a spacer etching process to form second spacers adjoined with said first spacers, said first and said second spacers having a generally equal height, wherein said second spacers remain associated with said first spacers and can be an etching protection mask in a subsequently applied self-aligned contact process.

Claim 17

A method for applying self-align contact technology to an electrically programmable read-only memory device, said method comprising: receiving a semiconductor substrate having said electrically programmable read-only device thereon, wherein said electrically programmable read-only memory device includes a plurality of spaced-apart gate structures and first spacers adjoined at the side of a subset of said plurality of spaced-apart gate structures; depositing a dielectric layer above said semiconductor substrate, said dielectric layer having two side regions, wherein said first spacers cover at least a part of said two side regions; applying a spacer etching process to form second spacers adjoined with said first spacers, said first and said second spacers having a generally equal height, wherein said second spacers remain associated with said first spacers and can be an etching protection mask in a subsequently applied self-aligned contact process.