Mos transistor with dual pocket implant

Claim 1

A method of producing an ULSI semiconductor device having an asymmetrical channel doping profile on a surface of a substrate for delaying a threshold voltage roll-off while minimizing a gate length, comprising the steps of: forming a gate oxide on the surface of the substrate; forming a gate on the gate oxide, the gate having a first side and a second side opposite from the first side; implanting a first dopant into the substrate with a 0° tilt, thereby performing a first pocket dopant implantation, and thereby forming a first source pocket adjacent to the gate first side and a drain pocket adjacent to the gate second side; asymmetrically implanting a second dopant into the substrate with a tilt in a range from 30° to 60°, thereby performing a second pocket dopant implantation, and thereby forming a second source pocket, said tilt being oriented from one of the two sides of the gate; implanting a source/drain extension dopant into the substrate with a 0° tilt, thereby performing a source/drain extension dopant implantation in a range of 1 to 3 KeV, thereby forming a source extension and a drain extension, and thereby forming said asymmetrical channel doping profile on said surface of said substrate, wherein said first, second and source/drain extension dopant comprise a same conductivity type, whereby said asymmetrical channel doping profile facilitates distancing a peak of said source pocket from a peak of said drain pocket for delaying said threshold voltage roll-off while minimizing said gate length; forming a dielectric spacer on the sides of the gate; annealing the substrate; and completing formation of said semiconductor device.

Claim 2

A method of producing an ULSI semiconductor device having an asymmetrical channel doping profile on a surface of a substrate for delaying a threshold voltage roll-off while minimizing a gate length, comprising the steps of: forming a gate oxide on the surface of the substrate; forming a gate on the gate oxide, the gate having a first side and a second side opposite from the first side; implanting a first dopant into the substrate with a 0° tilt, thereby performing a first pocket dopant implantation, and thereby forming a first source pocket adjacent to the gate first side and a drain pocket adjacent to the gate second side; asymmetrically implanting a second dopant into the substrate with a tilt in a range from 30° to 60°, thereby performing a second pocket dopant implantation, and thereby forming a second source pocket, said tilt being oriented from one of the two sides of the gate; implanting a source/drain extension dopant into the substrate with a 0° tilt, thereby performing a source/drain extension dopant implantation in a range of 1 to 3 KeV, thereby forming a source extension and a drain extension, and thereby forming said asymmetrical channel doping profile on said surface of said substrate, wherein said first, second and source/drain extension dopant comprise a same conductivity type, whereby said asymmetrical channel doping profile facilitates distancing a peak of said source pocket from a peak of said drain pocket for delaying said threshold voltage roll-off while minimizing said gate length; forming a dielectric spacer on the sides of the gate; annealing the substrate; and completing formation of said semiconductor device.

Claim 12

A method of producing an ULSI semiconductor device having an asymmetrical channel doping profile on a surface of a substrate for delaying a threshold voltage roll-off while minimizing a gate length, comprising the steps of: forming a gate oxide on the surface of the substrate; forming a gate on the gate oxide, the gate having a first side and a second side opposite from the first side; implanting a first dopant into the substrate with a 0° tilt, thereby performing a first pocket dopant implantation, and thereby forming a first source pocket adjacent to the gate first side and a drain pocket adjacent to the gate second side; initially annealing and driving said first dopant from the first pocket dopant implantation into the substrate; asymmetrically implanting a second dopant into the substrate with a tilt in a range from 30° to 60°, thereby performing a second pocket dopant implantation, and thereby forming a second source pocket, said tilt being oriented from one of the two sides of the gate; implanting a source/drain extension dopant into the substrate with a 0° tilt, thereby performing a source/drain extension dopant implantation, thereby forming a source extension and a drain extension, and thereby forming said asymmetrical channel doping profile on said surface of said substrate, whereby said asymmetrical channel doping profile facilitates distancing a peak of said source pocket from a peak of said drain pocket for delaying said threshold voltage roll-off while minimizing said gate length; forming a dielectric spacer on the sides of the gate; subjecting the substrate to a deep source/drain region dopant implantation with a 0° tilt, and thereby forming a source region and a drain region; annealing the substrate; etching at least one isolation trench into the surface of the substrate, said trenches being spaced apart from the dielectric spacer so that the source region extends from at least one isolation trench to said dielectric spacer; and completing formation of said semiconductor device, wherein the step of annealing the substrate comprises a rapid thermal annealing of said second dopant from the second pocket dopant implantation and said second source/drain extension dopant from the source/drain extension dopant implantation into the substrate, wherein said first pocket dopant implantation is performed with an implantation energy in a range from 5 keV to 10 keV, wherein said second pocket dopant implantation is performed with an implantation energy in a range from 10 keV to 20 keV, wherein said source/drain extension dopant implantation is performed with an implantation energy in a range from 1 keV to 3 keV, wherein said device comprises an N-channel MOSFET, wherein said first dopant comprises Boron (B), wherein said second dopant comprises Boron (B), and wherein said source/drain extension dopant comprises Boron (B), wherein said step of initially annealing and driving said first dopant is performed at a temperature in a range from 800° C. to 1000° C. before performing said second dopant implantation, wherein said step of rapid thermal annealing of said second dopant and said second source/drain extension dopant is performed at a temperature in a range from 1000° C. to 1200° C., and wherein said step of forming said dielectric spacer is performed at a temperature in a range less than 400° C.

Claim 13

A method of producing an ULSI semiconductor device having an asymmetrical channel doping profile on a surface of a substrate for delaying a threshold voltage roll-off while minimizing a gate length, comprising the steps of: forming a gate oxide on the surface of the substrate; forming a gate on the gate oxide, the gate having a first side and a second side opposite from the first side; implanting a first dopant into the substrate with a 0° tilt, thereby performing a first pocket dopant implantation, and thereby forming a first source pocket adjacent to the gate first side and a drain pocket adjacent to the gate second side; initially annealing and driving said first dopant from the first pocket dopant implantation into the substrate; asymmetrically implanting a second dopant into the substrate with a tilt in a range from 30° to 60°, thereby performing a second pocket dopant implantation, and thereby forming a second source pocket, said tilt being oriented from one of the two sides of the gate; implanting a source/drain extension dopant into the substrate with a 0° tilt, thereby performing a source/drain extension dopant implantation, thereby forming a source extension and a drain extension, and thereby forming said asymmetrical channel doping profile on said surface of said substrate, whereby said asymmetrical channel doping profile facilitates distancing a peak of said source pocket from a peak of said drain pocket for delaying said threshold voltage roll-off while minimizing said gate length; forming a dielectric spacer on the sides of the gate; subjecting the substrate to a deep source/drain region dopant implantation with a 0° tilt, and thereby forming a source region and a drain region; annealing the substrate; etching at least one isolation trench into the surface of the substrate, said trenches being spaced apart from the dielectric spacer so that the source region extends from at least one isolation trench to said dielectric spacer; and completing formation of said semiconductor device, wherein the step of annealing the substrate comprises a rapid thermal annealing of said second dopant from the second pocket dopant implantation and said second source/drain extension dopant from the source/drain extension dopant implantation into the substrate, wherein said first pocket dopant implantation is performed with an implantation energy in a range from 5 keV to 10 keV, wherein said second pocket dopant implantation is performed with an implantation energy in a range from 10 keV to 20 keV, wherein said source/drain extension dopant implantation is performed with an implantation energy in a range from 1 keV to 3 keV, wherein said device comprises an N-channel MOSFET, wherein said first dopant comprises Boron (B), wherein said second dopant comprises Boron (B), and wherein said source/drain extension dopant comprises Boron (B), wherein said step of initially annealing and driving said first dopant is performed at a temperature in a range from 800° C. to 1000° C. before performing said second dopant implantation, wherein said step of rapid thermal annealing of said second dopant and said second source/drain extension dopant is performed at a temperature in a range from 1000° C. to 1200° C., and wherein said step of forming said dielectric spacer is performed at a temperature in a range less than 400° C.