US6252268B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming transistors in a peripheral circuit of a semiconductor memory device
Assignee: Micron Technology Inc
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Filing: 1998-10-14
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Granted: 2001-06-26
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Expires: 2018-10-14
Abstract
Abstract A method of forming a transistor in a peripheral circuit of a random access memory device wherein a transistor gate, capacitor electrode or other component in the memory cell array is formed simultaneously with the formation of a transistor gate in the periphery.
Inventors
- 👤 Ceredig Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B10/00; H10B10/12; H10B10/18; H10B12/02; H10B12/05; H10B12/09; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
90 words
A random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region comprising a portion of the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a memory cell component in the array region comprising a portion of the second layer of polysilicon; and a periphery transistor gate in the peripheral region comprising a portion of the second layer of polysilicon.
Claim 2
Dependent Claim
90 words
A random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region comprising a portion of the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a memory cell component in the array region comprising a portion of the second layer of polysilicon; and a periphery transistor gate in the peripheral region comprising a portion of the second layer of polysilicon.
Claim 3
Dependent Claim
16 words
A device according to claim 1 , wherein the memory cell component comprises a load resistor.
Claim 4
Dependent Claim
17 words
A device according to claim 1 , wherein the memory cell component comprises a contact landing pad.
Claim 5
Dependent Claim
16 words
A device according to claim 1 , wherein the memory cell component comprises a capacitor electrode.
Claim 6
Dependent Claim
90 words
A static random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region comprising a portion of the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a load resistor in the array region comprising a portion of the second layer of polysilicon; and a periphery transistor gate in the peripheral region comprising a portion of the second layer of polysilicon.
Claim 7
Dependent Claim
90 words
A static random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region comprising a portion of the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a load resistor in the array region comprising a portion of the second layer of polysilicon; and a periphery transistor gate in the peripheral region comprising a portion of the second layer of polysilicon.
Claim 8
Dependent Claim
101 words
A static random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region in the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a third layer of polysilicon in the array region and in the peripheral region; a load resistor formed in at least the third layer of polysilicon in the array region; and a periphery transistor gate in the peripheral region formed in at least the third layer of polysilicon.
Claim 9
Dependent Claim
101 words
A static random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region in the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a third layer of polysilicon in the array region and in the peripheral region; a load resistor formed in at least the third layer of polysilicon in the array region; and a periphery transistor gate in the peripheral region formed in at least the third layer of polysilicon.
Claim 10
Dependent Claim
22 words
A device according to claim 6 , wherein the periphery transistor gate is formed in the third and second layers of polysilicon.
Claim 11
Dependent Claim
34 words
A device according to claim 6 , further comprising a first layer of polysilicon in the peripheral region and wherein the periphery transistor gate is formed in the third and first layers of polysilicon.
Claim 12
Dependent Claim
35 words
A device according to claim 7 , further comprising a first layer of polysilicon in the peripheral region and wherein the periphery transistor gate is formed in the third, second and first layers of polysilicon.
Claim 13
Dependent Claim
81 words
A dynamic random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region in the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a capacitor electrode in the array region in the second layer of polysilicon; and a periphery transistor gate in the peripheral region in the second layer of polysilicon.
Claim 14
Dependent Claim
81 words
A dynamic random access memory device, comprising: a memory cell array region and a peripheral region; a first layer of polysilicon in the array region; a memory transistor gate in the array region in the first layer of polysilicon; a second layer of polysilicon in the array region and in the peripheral region; a capacitor electrode in the array region in the second layer of polysilicon; and a periphery transistor gate in the peripheral region in the second layer of polysilicon.
Claim 15
Dependent Claim
16 words
A device according to claim 10 , wherein the capacitor electrode is a capacitor bottom electrode.
Claim 16
Dependent Claim
16 words
A device according to claim 10 , wherein the capacitor electrode is a capacitor top electrode.
Claim 17
Dependent Claim
39 words
A device according to claim 12 , further comprising a third layer of polysilicon between the first layer of polysilicon and the second layer of polysilicon and wherein a capacitor bottom electrode is formed in the third polysilicon layer.
References Cited (Backward Citations)
US4426764A
Cited
US4408385A
Cited
US4370798A
Cited
US5013678A
Cited
US4977099A
Cited
JPH03259566A
Cited
US5489791A
Cited
US5135881A
Cited
US5293336A
Cited
JPH04186877A
Cited
JPH04322459A
Cited
EP0522689A2
Cited
JPH0521805A
Cited
JPH05121700A
Cited
US5356826A
Cited
US5500387A
Cited
US5828096A
Cited
US5808335A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-25 | 2004-12-25 | 2005-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-25 | 2008-12-25 | 2009-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-25 | 2012-12-25 | 2013-06-26 | $7700.00 | Window Closed / Lapsed |