Patent US6239614B1 successfully refreshed from Google Patents.
US6239614B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Aquila Innovations Inc
•
Filing: 1999-04-01
•
Granted: 2001-05-29
•
Expires: 2019-04-01
Abstract
Abstract The present invention comprises first unit cells each including PMOS transistors and NMOS transistors, each transistor having a first threshold voltage, second unit cells each including PMOS transistors and NMOS transistors, each transistor having a second threshold voltage, a unit cell array comprised of the first and second unit cells laid in array form, a power switch disposed around the unit cell array and comprised of the PMOS transistors and NMOS transistors each having the second threshold voltage, and input/output circuits disposed around the unit cell array. Another invention comprises a first power supply line supplied with a first power supply potential level, a second power supply line supplied with a second power supply potential level, a first virtual power supply line, a second virtual power supply line, a latch circuit electrically connected between the first and second power supply lines, at least one logic circuit electrically connected between the first and second virtual power supply lines, a first capacitor electrically connected between the first power supply line and the first virtual power supply line, and a second capacitor electrically connected between the second power supply line and the second virtual power supply line.
Inventors
- 👤 Koichi Morikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D89/00; H10D89/10; H10D89/105
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
113 words
A semiconductor integrated circuit device, comprising: a plurality of first unit cells each including a plurality of first MOS transistors, each of the first MOS transistors having a first threshold voltage; a plurality of second unit cells each including a plurality of second MOS transistors, each of the second MOS transistors having a second threshold voltage; a unit cell array comprised of said first and second unit cells laid in array form; a power switch disposed around said unit cell array and comprised of a plurality of third MOS transistors, each of the third MOS transistors having the second threshold voltage; and a plurality of input/output circuits disposed around said unit cell array.
Claim 2
Dependent Claim
113 words
A semiconductor integrated circuit device, comprising: a plurality of first unit cells each including a plurality of first MOS transistors, each of the first MOS transistors having a first threshold voltage; a plurality of second unit cells each including a plurality of second MOS transistors, each of the second MOS transistors having a second threshold voltage; a unit cell array comprised of said first and second unit cells laid in array form; a power switch disposed around said unit cell array and comprised of a plurality of third MOS transistors, each of the third MOS transistors having the second threshold voltage; and a plurality of input/output circuits disposed around said unit cell array.
Claim 3
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 1 , wherein said power switch is turned off during standby and turned on when taken active.
Claim 4
Dependent Claim
23 words
The semiconductor integrated circuit device according to claim 1 , wherein parts of said power switch are disposed within said unit cell array.
Claim 5
Dependent Claim
134 words
A semiconductor integrated circuit device comprising: a first power supply line supplied with a first power supply potential level; a second power supply line supplied with a second power supply potential level; a first virtual power supply line; a second virtual power supply line; a latch circuit connected between said first and second power supply lines; a logic circuit connected between said first power supply line and said second virtual power supply line; a first capacitor connected between said first power supply line and said second virtual power supply line; and a second capacitor connected between said second power supply line and said first virtual power supply line; wherein said latch circuit, said logic circuit and said first and second capacitors are constructed by connecting MOS transistors placed within unit cells in array form.
Claim 6
Dependent Claim
134 words
A semiconductor integrated circuit device comprising: a first power supply line supplied with a first power supply potential level; a second power supply line supplied with a second power supply potential level; a first virtual power supply line; a second virtual power supply line; a latch circuit connected between said first and second power supply lines; a logic circuit connected between said first power supply line and said second virtual power supply line; a first capacitor connected between said first power supply line and said second virtual power supply line; and a second capacitor connected between said second power supply line and said first virtual power supply line; wherein said latch circuit, said logic circuit and said first and second capacitors are constructed by connecting MOS transistors placed within unit cells in array form.
Claim 7
Dependent Claim
96 words
The semiconductor integrated circuit device according to claim 4 , wherein said first capacitor is comprised of a first MOS transistor, which has a control electrode connected to said second virtual power supply line, and first and second electrodes commonly connected to said first power supply line, formed in a first conduction-type region; and wherein said second capacitor is comprised of a second MOS transistor, which has a control electrode connected to said first virtual power supply line, first and second electrodes commonly connected to said second power supply line, formed in a second conduction-type region.
Claim 8
Dependent Claim
97 words
The semiconductor integrated circuit device according to claim 4 , wherein said first capacitor is comprised of a first MOS transistor, which has a first electrode connected to said second virtual power supply line, and control and second electrodes commonly connected to said first power supply line, formed in a first conduction-type region; and wherein said second capacitor is comprised of a second MOS transistor, which has a first electrode connected to said first virtual power supply line, and control and second electrodes commonly connected to said second power supply line, formed in a second conduction-type region.
Claim 9
Dependent Claim
97 words
The semiconductor integrated circuit device according to claim 4 , wherein said first capacitor is comprised of a first MOS transistor, which has control and first electrodes commonly connected to said second virtual power supply line, and a second electrode connected to said first power supply line, formed in a first conduction-type region; and wherein said second capacitor is comprised of a second MOS transistor, which has control and first electrodes commonly connected to said first virtual power supply line, and a second electrode connected to said second power supply line, formed in a second conduction-type region.
References Cited (Backward Citations)
US5552618A
Cited
US5945702A
Cited
US5994726A
Cited
US5932900A
Cited
US6040609A
Cited
US6066866A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-28 | 2004-11-27 | 2005-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-28 | 2008-11-27 | 2009-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-28 | 2012-11-27 | 2013-05-29 | $7700.00 | Window Closed / Lapsed |