Multi-voltage-lever master-slice integrated circuit

Claim 1

A multi-voltage-level master-slice semiconductor integrated circuit device comprising: an input/output circuit section disposed about an edge of said device; said input/output circuit section having a substrate divided into a first substrate segment of a first conductivity type to which a first supply voltage is to be applied, a second substrate segment of said first conductivity type to which a second supply voltage is to be applied, and a third substrate segment of a second conductivity type to which a reference voltage is to be applied; said first substrate segment and said third substrate segment being electrically separated from each other; said second substrate segment and said third substrate segment being electrically separated from each other; a first input/output cell including said first, second and third substrate segments; said first input/output cell including a first input/output circuit having circuit elements disposed on only said first and third substrate segments of said first input/output cell; a second input/output cell including said first, second and third substrate segments; said second input/output cell including a second input/output circuit having circuit elements disposed on only said second and third substrate segments of said second input/output cell; and means for isolating said first and second voltage supplies including interposing said third substrate segment between said first and second substrate segments.