US4992845A
Expired / Lapsed
US
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Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line
Assignee: Mitsubishi Electric Corp
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Filing: 1989-01-06
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Granted: 1991-02-12
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Expires: 2009-01-06
Abstract
Abstract An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).
Inventors
- 👤 Takahiko Arakawa
- 👤 Kazuhiro Sakashita
- 👤 Satoru Kishida
- 👤 Toshiaki Hanibuchi
- 👤 Ichiro Tomioka
- 👤 Masahiro Ueda
- 👤 Yoshihiro Okuno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:12
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
168 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a single line in a direction from said bonding pads to said internal logic gate portion, wherein said transistor regions for output are positioned adjacent each other and said transistor regions for input and logic are positioned adjacent each other.
Claim 2
Dependent Claim
168 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a single line in a direction from said bonding pads to said internal logic gate portion, wherein said transistor regions for output are positioned adjacent each other and said transistor regions for input and logic are positioned adjacent each other.
Claim 3
Dependent Claim
53 words
The semiconductor integrated circuit device according to claim 1, wherein said first through fourth transistor regions being located in first through fourth positions, respectively, and disposed in a numerically sequential order, beginning with the first position, in a single line in a direction from said bonding pads to said internal logic gate portion.
Claim 4
Dependent Claim
42 words
The semiconductor integrated circuit device according to claim 2, wherein said first transistor region of the first conductivity type for output and said second transistor region of the second conductivity type for output are disposed in the second and first positions, respectively.
Claim 5
Dependent Claim
46 words
The semiconductor integrated circuit device according to claim 3, wherein said third transistor region of the first conductivity type for input and logic and said fourth transistor region of the second conductivity type for input and logic are disposed in the fourth and third positions, respectively.
Claim 6
Dependent Claim
46 words
The semiconductor integrated circuit device according to claim 2, wherein said third transistor region of the first conductivity type for input and logic and the fourth transistor region of the second conductivity type for input and logic are disposed in the fourth and third positions, respectively.
Claim 7
Dependent Claim
56 words
The semiconductor integrated circuit device according to claim 1, wherein said said third, fourth, first and second transistor regions being located in first through fourth positions respectively and disposed in a numerically sequential order, beginning with the first position, in a single line in the direction from said bonding pads to said internal logic gate portion.
Claim 8
Dependent Claim
46 words
The semiconductor integrated circuit device according to claim 6, wherein said third transistor region of the first conductivity type for input and logic and said fourth transistor region of the second conductivity type for input and logic are disposed in the second and first positions, respectively.
Claim 9
Dependent Claim
42 words
The semiconductor integrated circuit device according to claim 7, wherein said first transistor region of the first conductivity type for output and said second transistor region of the second conductivity type for output are disposed in the fourth and third positions respectively.
Claim 10
Dependent Claim
42 words
The semiconductor integrated circuit device according to claim 6, wherein said first transistor region of the first conductivity type for output and said second transistor region of the second conductivity type for output are disposed in the fourth and third positions, respectively.
Claim 11
Dependent Claim
230 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in that central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly and sequentially disposed in said first direction with respective transistors of said first conductivity type being paired with respective transistors of said second conductivity type to form functional output buffers, said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 12
Dependent Claim
230 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in that central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly and sequentially disposed in said first direction with respective transistors of said first conductivity type being paired with respective transistors of said second conductivity type to form functional output buffers, said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 13
Dependent Claim
46 words
The semiconductor integrated circuit device according to claim 10, wherein each of transistors formed in said first transistor region of the first conductivity type for output and said second transistor region of the second conductivity type for output has the same shape on said semiconductor chip.
Claim 14
Dependent Claim
48 words
The semiconductor integrated circuit device according to claim 10, wherein a plurality of transistors formed in said first transistor region of the first conductivity type for output and said second transistor region of the second conductivity type for output are operatively connected to each other through metal interconnections.
Claim 15
Dependent Claim
236 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly and sequentially disposed in a second direction perpendicularly intersecting said first direction with the individual transistors of said first conductivity type being paired with individual transistors of said second conductivity type to form functional output buffers; said transistor regions for output being positioned adjacent each other and said transistor regions for input and log being positioned adjacent each other.
Claim 16
Dependent Claim
236 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly and sequentially disposed in a second direction perpendicularly intersecting said first direction with the individual transistors of said first conductivity type being paired with individual transistors of said second conductivity type to form functional output buffers; said transistor regions for output being positioned adjacent each other and said transistor regions for input and log being positioned adjacent each other.
Claim 17
Dependent Claim
239 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said third transistor region of the first conductivity type for input and logic and a plurality of transistor in said fourth transistor region of the second conductivity type for input and logic being regularly and sequentially arranged in a second direction perpendicularly intersecting said first direction with respective transistors of said first conductivity type being paired with respective transistors of said second conductivity type to form functional input/logic buffers; said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 18
Dependent Claim
239 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said third transistor region of the first conductivity type for input and logic and a plurality of transistor in said fourth transistor region of the second conductivity type for input and logic being regularly and sequentially arranged in a second direction perpendicularly intersecting said first direction with respective transistors of said first conductivity type being paired with respective transistors of said second conductivity type to form functional input/logic buffers; said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 19
Dependent Claim
51 words
The semiconductor integrated circuit device according to claim 14, wherein each of the transistors in said third transistor region for of the first conductivity type for input and logic and said fourth transistor region of the second conductivity type for input and logic has the same shape on said semiconductor chip.
Claim 20
Dependent Claim
53 words
The semiconductor integrated circuit device according to claim 14, wherein a plurality of the transistors formed in said third transistor region of the first conductivity type for input and logic and said fourth transistor region of the second conductivity type for input and logic are operatively connected to each other through metal interconnections.
Claim 21
Dependent Claim
279 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly disposed in said first direction with respective transistors of said first conductivity type being paired with respective transistors of said second conductivity type to form functional output buffers; a plurality of transistors in said third transistor region of the first conductivity type for input and logic and a plurality of transistors in said fourth transistor region of the second conductivity type for input and logic being regularly and sequentially arranged in a second direction perpendicularly intersecting said first direction; said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 22
Dependent Claim
279 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly disposed in said first direction with respective transistors of said first conductivity type being paired with respective transistors of said second conductivity type to form functional output buffers; a plurality of transistors in said third transistor region of the first conductivity type for input and logic and a plurality of transistors in said fourth transistor region of the second conductivity type for input and logic being regularly and sequentially arranged in a second direction perpendicularly intersecting said first direction; said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 23
Dependent Claim
280 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly and sequentially disposed in a second direction perpendicularly intersecting said first direction with respective transistors of said conductivity type being paired with respective transistors of said second conductivity type to form functional output buffers; a plurality of transistors in said third transistor region of the first conductivity type for input and logic and a plurality of transistors in said fourth transistor region of the second conductivity type for input and logic being regularly and sequentially arranged in said second direction; said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 24
Dependent Claim
280 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic, the first through fourth transistor regions being disposed in a first direction from said bonding pads to said internal logic gate portion; a plurality of transistors in said first transistor region of the first conductivity type for output and a plurality of transistors in said second transistor region of the second conductivity type for output being regularly and sequentially disposed in a second direction perpendicularly intersecting said first direction with respective transistors of said conductivity type being paired with respective transistors of said second conductivity type to form functional output buffers; a plurality of transistors in said third transistor region of the first conductivity type for input and logic and a plurality of transistors in said fourth transistor region of the second conductivity type for input and logic being regularly and sequentially arranged in said second direction; said transistor regions for output being positioned adjacent each other and said transistor regions for input and logic being positioned adjacent each other.
Claim 25
Dependent Claim
229 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic; a continuous power supply bus formed over said first transistor region of said first conductivity type for output on all said output buffer cells within each said input/output buffer, said continuous power supply bus disposed in a direction perpendicular to a direction from said bonding pads to said internal logic gate portion; and a continuous ground bus formed adjacent said continuous power supply bus and over said second transistor region of said second conductivity type for output on all said output buffer cells within each input/output buffer, said continuous ground bus disposed in a direction perpendicular to a direction from said bonding pads to said internal logic gate portion.
Claim 26
Dependent Claim
229 words
A semiconductor integrated circuit device comprising: an internal logic gate portion provided in the central portion of a semiconductor chip; an input/output buffer in which a plurality of input/output buffer cells are provided to surround said internal logic gate portion; and a plurality of bonding pads respectively provided in the peripheral portions of said semiconductor chip corresponding to said plurality of input/output buffer cells; each of said input/output buffer cells comprising a first transistor region of a first conductivity type for output, a second transistor region of a second conductivity type for output, a third transistor region of the first conductivity type for input and logic, and a fourth transistor region of the second conductivity type for input and logic; a continuous power supply bus formed over said first transistor region of said first conductivity type for output on all said output buffer cells within each said input/output buffer, said continuous power supply bus disposed in a direction perpendicular to a direction from said bonding pads to said internal logic gate portion; and a continuous ground bus formed adjacent said continuous power supply bus and over said second transistor region of said second conductivity type for output on all said output buffer cells within each input/output buffer, said continuous ground bus disposed in a direction perpendicular to a direction from said bonding pads to said internal logic gate portion.
Claim 27
Dependent Claim
279 words
A semiconductor integrated circuit comprising an internal logic gate portion provided in the central portion of a semiconductor chip, a plurality of bonding pads provided at the peripheral portions of the semiconductor chip, and a plurality of input/output buffer cells provided between the logic gate portion and the bonding pads, each input/output buffer cell corresponding to a bonding pad, the input/output buffer cells each comprising regions of a first conductivity type for output and input and logic and regions, of a second conductivity type for input and output and logic, all said regions being arranged in a single line in first direction from the bonding pads to the logic gate portion, characterized in that the regions of the first conductivity type comprises a first transistor region of the first conductivity type for output and a second transistor region of the first conductivity type for input and logic being isolated from the first transistor region, that the regions of the second conductivity type comprises a third transistor region of the second conductivity type for output adjacent to the first transistor region and a fourth transistor region of the second conductivity type for input and logic isolated from the third transistor region and adjacent to the second transistor region, individual transistors of regions of the first conductivity type having the same shape on said semiconductor chip and being disposed in the same direction and individual transistors of regions of the second conductivity type having the same shape on said semiconductor chip and being arranged in the same direction, and that the first through fourth transistor regions are arranged in a line from a corresponding bonding pad to the logic gate portion.
Claim 28
Dependent Claim
279 words
A semiconductor integrated circuit comprising an internal logic gate portion provided in the central portion of a semiconductor chip, a plurality of bonding pads provided at the peripheral portions of the semiconductor chip, and a plurality of input/output buffer cells provided between the logic gate portion and the bonding pads, each input/output buffer cell corresponding to a bonding pad, the input/output buffer cells each comprising regions of a first conductivity type for output and input and logic and regions, of a second conductivity type for input and output and logic, all said regions being arranged in a single line in first direction from the bonding pads to the logic gate portion, characterized in that the regions of the first conductivity type comprises a first transistor region of the first conductivity type for output and a second transistor region of the first conductivity type for input and logic being isolated from the first transistor region, that the regions of the second conductivity type comprises a third transistor region of the second conductivity type for output adjacent to the first transistor region and a fourth transistor region of the second conductivity type for input and logic isolated from the third transistor region and adjacent to the second transistor region, individual transistors of regions of the first conductivity type having the same shape on said semiconductor chip and being disposed in the same direction and individual transistors of regions of the second conductivity type having the same shape on said semiconductor chip and being arranged in the same direction, and that the first through fourth transistor regions are arranged in a line from a corresponding bonding pad to the logic gate portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-02-11 | 1994-08-13 | 1995-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-11 | 1998-08-13 | 1999-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-11 | 2002-08-13 | 2003-02-12 | $7700.00 | Window Closed / Lapsed |