Semiconductor integrated circuit device having an improved buffer arrangement

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits; a plurality of bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell; and wiring leads which serve to interconnect MISFETs of said each unit cell to form one of an input circuit and an output circuit and which include an interconnection with an adjacent bonding pad, said MISFETs being arranged such that a predetermined MISFET in each of said unit cells will form a protective MISFET connected to other MISFETs in the unit cell and between an adjacent bonding pad and a predetermined reference potential to prevent destruction of any of said other MISFETs whose gate electrode is supplied with a signal from the bonding pad in said unit cells interconnected to form an input circuit.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein the predetermined MISFET is an n-channel MOSFET.

Claim 4

A semiconductor integrated circuit device according to claim 1, wherein said MISFETs include n-channel MISFETs and p-channel MISFETs, and said predetermined MISFET is an n-channel MISFET.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein said predetermined MISFET is coupled with a p-channel MISFET to form an inverter of a final output stage in said unit cell forming said output circuit.

Claim 6

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits; a plurality of bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell; and wiring leads which serve to interconnect MISFETs of said each unit cell to form one of an input circuit and an output circuit and which include an interconnection with an adjacent bonding pad, wherein said predetermined MISFETs are arranged such that in each of said unit cells at least two of said predetermined MISFETs are connected electrically in parallel by said wiring leads, have gate electrodes geometrically parallel to each other, and share semiconductor regions functioning as source or drain regions with the MISFETs adjoining them.

Claim 7

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits; a plurality of bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell; and wiring leads which serve to interconnect MISFETs of said each unit cell to form one of an input circuit and an output circuit and which include an interconnection with an adjacent bonding pad, wherein said predetermined MISFETs are arranged such that in each of said unit cells at least two of said predetermined MISFETs are connected electrically in parallel by said wiring leads, have gate electrodes geometrically parallel to each other, and share semiconductor regions functioning as source or drain regions with the MISFETs adjoining them.

Claim 8

A semiconductor integrated circuit device according to claim 5, wherein said at least two MISFETs connected electrically in parallel have gate electrodes of substantially the same shape and have substantially equal channel lengths and channel widths.

Claim 9

A semiconductor integrated circuit device according to claim 6, wherein the at least two parallel-connected MISFETs form a protective MISFET connected to other MISFETs in the unit cell and between an adjacent bonding pad and a predetermined reference potential to prevent destruction of said other MISFETs in said unit cells interconnected to form an input circuit.

Claim 10

A semiconductor integrated circuit device according to claim 7, wherein said MISFETs include n-channel MISFETs and p-channel MISFETs, said protective MISFET is comprised of the n-channel MISFETs, and wherein each of the parallel-connected MISFETs is coupled with a p-channel MISFET to form an inverter of a final output stage in said unit cells interconnected to form an output circuit.

Claim 11

A semiconductor integrated circuit device according to claim 5, wherein the parallel-connected MISFETs include a first group of MISFETs which have gate electrodes of substantially the same shape and have substantially equal channel lengths and channel widths, and second groups of MISFETs which have gate electrodes of substantially the same shape of gate electrodes and have substantially equal channel lengths and channel widths, wherein the channel widths of said second group of MISFETs are smaller than those of said first group of MISFETs.

Claim 12

A semiconductor integrated circuit device according to claim 9, wherein said first group of MISFETs constitute a protective MISFET, and said second group of MISFETs provide another part of the input circuit in said unit cells interconnected to form an input circuit, said protective MISFET preventing destruction of said second group of MISFETs whose gate electrodes are supplied with a signal from an adjacent bonding pad, and further wherein said first group of MISFETs constitute a part of an inverter of a final output stage, and said second group of MISFETs provide another part of the output circuit in said unit cells interconnected to form an output circuit.

Claim 13

A semiconductor integrated circuit device according to claim 10, wherein said each second group is comprised of two MISFETs.

Claim 14

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including n-channel MISFETs and p-channel MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits, said n-channel MISFETs, before being interconnected, have a dual identity of both input and output possible circuits. said n-channel MISFETs and p-channel MISFETs including groups each comprised of a plurality of n-channel MISFETs and groups each comprised of a plurality of p-channel MISFETs, said MISFETs of said groups being formed so as to have gate electrodes geometrically parallel to each other and to share semiconductor regions as source or drain regions with the MISFETs adjoining each other; a plurality of bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell; and wiring leads which serve to interconnect MISFETs of said each unit cell to form one of an input circuit and an output circuit and which include an interconnection with an adjacent bonding pad, wherein said MISFETs are arranged such that a first group comprised of a plurality of n-channel MISFETs connected electrically in parallel with each other will form a protective MISFET connected to other MISFETs in said unit cell and between an adjacent bonding pad and a predetermined reference potential to prevent destruction of any of said other MISFETs whose gate electrodes are supplied with a signal from the bonding pad in said unit cells interconnected to form an input circuit; and wherein the same first group comprised of the plurality of n-channel MISFETs and a second group comprised of a plurality of p-channel MISFETs, said plurality of n-channel MISFETs and p-channel MISFETs being respectively connected electrically in parallel with each other, will form an inverter of a final output stage in said unit cells interconnected to form an output circuit.

Claim 15

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including n-channel MISFETs and p-channel MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits, said n-channel MISFETs, before being interconnected, have a dual identity of both input and output possible circuits. said n-channel MISFETs and p-channel MISFETs including groups each comprised of a plurality of n-channel MISFETs and groups each comprised of a plurality of p-channel MISFETs, said MISFETs of said groups being formed so as to have gate electrodes geometrically parallel to each other and to share semiconductor regions as source or drain regions with the MISFETs adjoining each other; a plurality of bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell; and wiring leads which serve to interconnect MISFETs of said each unit cell to form one of an input circuit and an output circuit and which include an interconnection with an adjacent bonding pad, wherein said MISFETs are arranged such that a first group comprised of a plurality of n-channel MISFETs connected electrically in parallel with each other will form a protective MISFET connected to other MISFETs in said unit cell and between an adjacent bonding pad and a predetermined reference potential to prevent destruction of any of said other MISFETs whose gate electrodes are supplied with a signal from the bonding pad in said unit cells interconnected to form an input circuit; and wherein the same first group comprised of the plurality of n-channel MISFETs and a second group comprised of a plurality of p-channel MISFETs, said plurality of n-channel MISFETs and p-channel MISFETs being respectively connected electrically in parallel with each other, will form an inverter of a final output stage in said unit cells interconnected to form an output circuit.

Claim 16

A semiconductor integrated circuit device according to claim 12, wherein the input circuit operation except said protective MISFET and the output circuit operation except the final-stage inverter are provided by other groups comprised of the plurality of n-channel MISFETs and other groups comprised of the plurality of p-channel MISFETs than the aforementioned first and second groups, and each of the other groups is comprised of two MISFETs which have gate electrodes physically parallel to each other and which share a semiconductor region functioning as a source or drain region.

Claim 17

A semiconductor integrated circuit device according to claim 13, wherein channel widths of the MISFETs of said first and second groups are greater than channel widths of the MISFETs of the other groups.

Claim 18

A semiconductor integrated circuit device according to claim 14, wherein said first and second MISFETs have gate electrodes of the same shape.

Claim 19

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits, said MISFETs including groups each comprised of a plurality of MISFETs which are formed so as to have gate electrodes geometrically parallel to each other and to share semiconductor regions as source or drain regions with the MISFETs adjoining each other; and bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell.

Claim 20

A semiconductor integrated circuit device comprising: a semiconductor substrate; a logic circuit portion formed at a predetermined location of said semiconductor substrate; a plurality of unit cells which are formed at a predetermined location of said semiconductor substrate, each said unit cell including MISFETs which are interconnected in order to form one of an input circuit and an output circuit for said logic circuit portion independently of interconnections made for others of said plurality of unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits, said MISFETs including groups each comprised of a plurality of MISFETs which are formed so as to have gate electrodes geometrically parallel to each other and to share semiconductor regions as source or drain regions with the MISFETs adjoining each other; and bonding pads which are formed on said semiconductor substrate so that each bonding pad is adjacent to a predetermined unit cell.

Claim 21

A semiconductor integrated circuit device according to claim 16, wherein said groups each comprised of the plurality of MISFETs include a first group comprised of MISFETs which have equal channel widths, and other groups each comprised of MISFETs which have equal channel widths smaller than channel widths of said MISFETs of said first group.

Claim 22

A semiconductor integrated circuit device according to claim 17, wherein said first group is comprised of at least three MISFETs, and each of the other groups is comprised of two MISFETs.

Claim 23

A semiconductor integrated circuit device according to claim 16, wherein said MISFETs include n-channel MISFETs and p-channel MISFETs, and said groups each comprised of the plurality of MISFETs include a first group comprised of n-channel MISFETs which have equal channel widths, a second group comprised of p-channel MISFETs which have equal channel widths, third groups each comprised of MISFETs which have equal channel widths smaller than channel widths of said MISFETs of said first group, and fourth groups each comprised of MISFETs which have equal channel widths smaller than channel widths of said MISFETs of said each third group.

Claim 24

A semiconductor integrated circuit device according to claim 19, wherein each of said first and second groups is comprised of at least three MISFETs, and each of said third and fourth groups is comprised of two MISFETs.

Claim 25

A semiconductor integrated circuit device according to claim 20, wherein said MISFETs of said first and second groups have gate electrodes parallel to each other and have equal channel widths, and said MISFETs of said third and fourth groups are arranged between said first and second groups with said third group adjoining said first group and with said fourth group adjoining said second group.

Claim 26

A semiconductor integrated circuit device according to claim 21, wherein said MISFETs of said third and fourth groups have gate electrodes which extend orthogonally to a direction in which the gate electrodes of said MISFETs of said first and second groups extend.

Claim 27

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of unit cells which are identical except for wiring patterns on the substrate, each unit cell having a plurality of MISFETs; a plurality of bonding pads formed on said semiconductor substrate with each bonding pad being adjacent to a single respective unit cell to form a plurality of bonding pad-unit cell pairs each comprised of a single bonding pad and a single unit cell; wiring leads for interconnecting said bonding pads to said unit cells, and including an interconnection for at least some of said MISFETs of said unit cells so that each unit cell forms one of an input circuit and an output circuit independently of the interconnections made for other unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits, and wherein at least one first MISFET in each of said unit cells forming said input circuit has a corresponding at least one first MISFET in each of said unit cells forming said output circuit.

Claim 28

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of unit cells which are identical except for wiring patterns on the substrate, each unit cell having a plurality of MISFETs; a plurality of bonding pads formed on said semiconductor substrate with each bonding pad being adjacent to a single respective unit cell to form a plurality of bonding pad-unit cell pairs each comprised of a single bonding pad and a single unit cell; wiring leads for interconnecting said bonding pads to said unit cells, and including an interconnection for at least some of said MISFETs of said unit cells so that each unit cell forms one of an input circuit and an output circuit independently of the interconnections made for other unit cells, wherein said MISFETs, before being interconnected, have a dual identity of both input and output possible circuits, and wherein at least one first MISFET in each of said unit cells forming said input circuit has a corresponding at least one first MISFET in each of said unit cells forming said output circuit.

Claim 29

A semiconductor integrated circuit device according to claim 23, wherein said one first MISFET in said unit cells forming said input circuit is connected with predetermined elements in said unit cells to form a protective MISFET and said one first MISFET in said unit cells forming said output circuit is connected with predetermined elements in said unit cells to form an inverter of a final output stage.

Claim 30

A semiconductor integrated circuit device according to claim 1, wherein said bonding pads are arranged so that each bonding pad is adjacent to a single respective unit cell so that a plurality of bonding pad-unit cell pairs are formed with each of said bonding pad-unit cell pairs consisting of a single bonding pad and a single unit cell.

Claim 31

A semiconductor integrated circuit device according to claim 5, wherein said bonding pads are arranged so that each bonding pad is adjacent to a single respective unit cell so that a plurality of bonding pad-unit cell pairs are formed with each of said bonding pad-unit cell pairs consisting of a single bonding pad and a single unit cell.

Claim 32

A semiconductor integrated circuit device according to claim 12, wherein said bonding pads are arranged so that each bonding pad is adjacent to a single respective unit cell so that a plurality of bonding pad-unit cell pairs are formed with each of said bonding pad-unit cell pairs consisting of a single bonding pad and a single unit cell.

Claim 33

A semiconductor integrated circuit device according to claim 16, wherein said bonding pads are arranged so that each bonding pad is adjacent to a single respective unit cell so that a plurality of bonding pad-unit cell pairs are formed with each of said bonding pad-unit cell pairs consisting of a single bonding pad and a single unit cell.