EP0023818A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device including a master slice and method of making the same
Assignee: Fujitsu Ltd
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Filing: 1980-07-30
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Granted: —
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Expires: 2000-07-30
Abstract
Abstract A semiconductor integrated circuit device includes a master slice comprising a number of basic semiconductor elements (EM) arranged in a regular array of columns and rows, and wiring conductors (LS and LL) arranged in columns or rows between the basic semiconductor elements (Figure 4). This master slice is used to prepare a semiconductor integrated circuit device to perform a particular logic operation by cutting the wiring conductors (LS and LL) at (CP) and, or establishing contacts (ℓ 1 , ℓ 2 , ℓ 3 ) between the wiring conductors and the basic semiconductor elements (EM) to interconnect them (Figure 5).
Inventors
- 👤 Yoshihide Sugiura
- 👤 Hiroaki Ichikawa
- 👤 Nobutake Matsumura
- 👤 Nobuo Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 02:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10W; H10W20/00; H10W20/20; H10W20/40; H10W20/49
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
74 words
A semiconductor integrated circuit device comprising a master slice containing a number of basic semiconductor elements arranged in a regular array of columns and rows, and wiring conductors arranged in columns or rows between the basic semiconductor elements, the wiring conductors being cut and, or having contacts formed with them to provide wiring to interconnect the basic semiconductor elements, so that an integrated circuit chip capable of performing a required logic operation is obtained.
Claim 2
Dependent Claim
74 words
A semiconductor integrated circuit device comprising a master slice containing a number of basic semiconductor elements arranged in a regular array of columns and rows, and wiring conductors arranged in columns or rows between the basic semiconductor elements, the wiring conductors being cut and, or having contacts formed with them to provide wiring to interconnect the basic semiconductor elements, so that an integrated circuit chip capable of performing a required logic operation is obtained.
Claim 3
Dependent Claim
57 words
A semiconductor integrated circuit device according to claim 1, wherein the wiring conductors comprise a plurality of first wiring conductors formed between adjacent basic semiconductor elements in a column or row, and a plurality of second wiring conductors formed between adjacent columns or rows of the basic semiconductor elements and extending in the direction of the columns.
Claim 4
Dependent Claim
119 words
A semiconductor integrated circuit device according to claim 1 or claim 2, wherein the basic semiconductor elements are each formed by a pair of CMOS elements which comprise a first diffusion layer including three n+-type diffusion layers acting as source or drain regions and two p-type regions, each p-ty: ' e region being sandwiched between two of the n+-t pe diffusion layers, a second diffusion layer including three p+-type diffusion layers acting as source or drain regions and two n-type regions, each n-type region being sandwiched between two of the p+-type diffusion layers and first and second polycrystalline silicon layers extending parallel to each other over the first and second diffusion layers, the polycrystalline silicon layers forming gate electrodes.
Claim 5
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 3, wherein the wiring conductors are formed by diffusion layers formed simultaneously with the first and second diffusion layers.
Claim 6
Dependent Claim
29 words
A semiconductor integrated circuit device according to claim 3, wherein the wiring conductors are formed by polycrystalline silicon layers formed simultaneously with the first and second polycrystalline silicon layers.
Claim 7
Dependent Claim
46 words
A master slice for forming a semiconductor integrated circuit device having a number of basic semiconductor elements arranged in a regular array of columns and rows characterised in that the master slice also includes wiring conductors arranged in columns or rows between the basic semiconductor elements.
Claim 8
Dependent Claim
46 words
A master slice for forming a semiconductor integrated circuit device having a number of basic semiconductor elements arranged in a regular array of columns and rows characterised in that the master slice also includes wiring conductors arranged in columns or rows between the basic semiconductor elements.
Claim 9
Dependent Claim
58 words
A master slice according to claim 6, further characterised in that the wiring conductors comprise a plurality of first wiring conductors formed between adjacent basic semiconductor elements in a column or row, and a plurality of second wiring conductors formed between adjacent columns or rows of the basic semiconductor elements and extending in the direction of the columns.
Claim 10
Dependent Claim
28 words
A master slice according to claim 6 or 7, further characterised in that the basic semiconductor elements and the wiring conductors are all electrically insulated from one another.
Claim 11
Independent Claim
91 words
A method of making a semiconductor integrated circuit device comprising the steps of: a) providing a master slice containing a number of basic semiconductor elements arranged in a regular array of columns and rows, and wiring conductors arranged in columns or rows between the basic semiconductor elements; and, b) cutting at least some of the wiring conductors and, or establishing contact between at least some of the wiring conductors and at least some of the basic semiconductor elements to interconnect the basic semiconductor elements to form the required logic circuit elements.
Claim 12
Independent Claim
91 words
A method of making a semiconductor integrated circuit device comprising the steps of: a) providing a master slice containing a number of basic semiconductor elements arranged in a regular array of columns and rows, and wiring conductors arranged in columns or rows between the basic semiconductor elements; and, b) cutting at least some of the wiring conductors and, or establishing contact between at least some of the wiring conductors and at least some of the basic semiconductor elements to interconnect the basic semiconductor elements to form the required logic circuit elements.
References Cited (Backward Citations)
No citation records indexed.
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