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US6040609A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for integrating, in a single semiconductor chip, MOS technology devices with different threshold voltages

Assignee: STMicroelectronics SRL
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Filing: 1998-10-23
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Granted: 2000-03-21
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Expires: 2018-10-23
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Abstract

Abstract Process for integrating in a same MOS technology devices with different threshold voltages. Simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area. Selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions. Said two MOS devices consequently have respective threshold voltages that depend on the corner density for unit area and on the aperture angles of the corner of the respective gate electrodes.

Inventors

  • 👤 Ferruccio Frisina
  • 👤 Davide Bolognesi
  • 👤 Angelo Magri'

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 15:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/013; H10D84/0135; H10D84/014; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D62/17; H10D62/393

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 156 words
A process for integrating in a same MOS technology devices with different threshold voltages, comprising: simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density per unit area; and selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density per unit area and on the aperture angles of the corner of the respective gate electrodes.
Claim 2
Dependent Claim 156 words
A process for integrating in a same MOS technology devices with different threshold voltages, comprising: simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density per unit area; and selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density per unit area and on the aperture angles of the corner of the respective gate electrodes.
Claim 3
Dependent Claim 29 words
The process of claim 1 wherein said selective introduction of dopant comprises dopant implantation performed using as a mask the gate electrodes, and a subsequent diffusion of the dopant.
Claim 4
Dependent Claim 15 words
The process of claim 1 wherein said MOS technology power devices are vertical MOS transistors.
Claim 5
Dependent Claim 15 words
The process of claim 1 wherein said MOS technology power devices are horizontal MOS transistors.
Claim 6
Dependent Claim 22 words
The process of claim 1 wherein said MOS technology devices integrated in the same semiconductor chip are vertical and horizontal MOS transistors.
Claim 7
Dependent Claim 76 words
A semiconductor chip having at least two integrated MOS devices with different threshold voltages, each one comprising a respective gate electrode superimposed over a respective channel region, each gate electrode comprising substantially rectilinear portions and corners, and respective source and drain electrodes separated by said channel region, wherein said threshold voltages of the two MOS devices depends on the corner density per unit area and on the aperture angles of the corners of each gate electrode.
Claim 8
Dependent Claim 76 words
A semiconductor chip having at least two integrated MOS devices with different threshold voltages, each one comprising a respective gate electrode superimposed over a respective channel region, each gate electrode comprising substantially rectilinear portions and corners, and respective source and drain electrodes separated by said channel region, wherein said threshold voltages of the two MOS devices depends on the corner density per unit area and on the aperture angles of the corners of each gate electrode.
Claim 9
Independent Claim 211 words
A method for creating devices disposed on a single semiconductor material having different threshold voltages, comprising: forming a first gate electrode overlaying the semiconductor material, the first gate electrode having a first corner density and an aperture angle for each corner; forming a second gate electrode overlaying the semiconductor material substantially simultaneously with the forming of the first gate electrode, the second gate electrode having a second corner density and an aperture angle for each corner, at least one of the second corner density and aperture angle for a corner of the second gate electrode being respectively different than the first corner density and aperture angle for the first gate electrode; and doping the semiconductor material with a dopant in areas not overlaid by the first and second gate electrodes, the dopant being disposed at least in part in portions of the semiconductor material overlaid by the first and second gate electrode, a concentration of the dopant in the semiconductor material overlaid by the first and second gate electrodes respectively corresponding to the corner density and aperture angle of corners of the first and second gate electrodes, the threshold voltage of the devices respectively corresponding to the dopant concentrations of the semiconductor material overlaid by the first and second gate electrodes.
Claim 10
Independent Claim 211 words
A method for creating devices disposed on a single semiconductor material having different threshold voltages, comprising: forming a first gate electrode overlaying the semiconductor material, the first gate electrode having a first corner density and an aperture angle for each corner; forming a second gate electrode overlaying the semiconductor material substantially simultaneously with the forming of the first gate electrode, the second gate electrode having a second corner density and an aperture angle for each corner, at least one of the second corner density and aperture angle for a corner of the second gate electrode being respectively different than the first corner density and aperture angle for the first gate electrode; and doping the semiconductor material with a dopant in areas not overlaid by the first and second gate electrodes, the dopant being disposed at least in part in portions of the semiconductor material overlaid by the first and second gate electrode, a concentration of the dopant in the semiconductor material overlaid by the first and second gate electrodes respectively corresponding to the corner density and aperture angle of corners of the first and second gate electrodes, the threshold voltage of the devices respectively corresponding to the dopant concentrations of the semiconductor material overlaid by the first and second gate electrodes.
Claim 11
Dependent Claim 47 words
The method of claim 7 wherein doping the semiconductor material comprises: implanting the dopant into portions of the semiconductor material not overlaid by the first and second gate electrodes; and diffusing the dopant into portions of the semiconductor material overlaid by the first and second gate electrodes.
Claim 12
Dependent Claim 18 words
The method of claim 7 wherein the first and second gate electrodes comprise gate electrodes for horizontal transistors.
Claim 13
Dependent Claim 18 words
The method of claim 7 wherein the first and second gate electrodes comprise gate electrodes for vertical transistors.
Claim 14
Dependent Claim 24 words
The method of claim 7 wherein the first and second gate electrodes comprise gate electrodes for a horizontal transistor and a vertical transistor respectively.
Claim 15
Dependent Claim 18 words
The method of claim 7 wherein the aperture angles comprise angles less than or equal to 180 degrees.
Claim 16
Dependent Claim 18 words
The method of claim 7, further comprising: forming a source and a drain for each of the devices.
Claim 17
Dependent Claim 30 words
The method of claim 7 wherein the portion of the semiconductor material having the dopant that is overlaid by the first and second gate electrodes comprises conducting channels of transistors.
Claim 18
Independent Claim 136 words
A method for doping a semiconductor material with varying doping concentrations, comprising: determining a doping profile for the semiconductor material; matching a geometry of a mask to the doping profile, the mask having a relatively high corner density per unit area in a portion of the semiconductor material that is to have a relatively low doping concentration and having a relatively low corner density per unit area in a portion of the semiconductor material that is to have a relatively high doping concentration; masking the semiconductor material with the mask; implanting a dopant into portions of the semiconductor material not covered by the mask; and diffusing the dopant into portions of the semiconductor material covered by the mask, the doping concentration of the diffused dopant corresponding to the corner density per unit area of the mask.
Claim 19
Independent Claim 136 words
A method for doping a semiconductor material with varying doping concentrations, comprising: determining a doping profile for the semiconductor material; matching a geometry of a mask to the doping profile, the mask having a relatively high corner density per unit area in a portion of the semiconductor material that is to have a relatively low doping concentration and having a relatively low corner density per unit area in a portion of the semiconductor material that is to have a relatively high doping concentration; masking the semiconductor material with the mask; implanting a dopant into portions of the semiconductor material not covered by the mask; and diffusing the dopant into portions of the semiconductor material covered by the mask, the doping concentration of the diffused dopant corresponding to the corner density per unit area of the mask.
Claim 20
Dependent Claim 17 words
The method of claim 15 wherein the corner density comprises the number of corners per unit area.
Claim 21
Dependent Claim 20 words
The method of claim 15 wherein the corner density corresponds to aperture angles of the respective corners of the mask.
Claim 22
Dependent Claim 18 words
The method of claim 17 wherein the aperture angles comprise angles less than or equal to 180 degrees.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-03-21 2003-09-20 2004-03-21 $2000.00 Window Closed / Lapsed
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