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US6235630B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Silicide pattern structures and methods of fabricating the same

Assignee: Micron Technology Inc
•
Filing: 1998-08-19
•
Granted: 2001-05-22
•
Expires: 2018-08-19
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Abstract

Abstract Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Inventors

  • 👤 Salman Akram
  • 👤 Y. Jeff Hu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 04:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/047; G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07314; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/01125; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/414; H10W20/033; H10W20/071; H10W20/081; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10B12/30; H10B12/48; H10B12/485; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/952

Claims Analysis

Total Claims: 45
Claim 1
Independent Claim 162 words
A method of forming a contact interface, comprising: providing a semiconductor substrate having at least one active-device region; forming a dielectric layer over said semiconductor substrate; forming a barrier layer over said dielectric layer; etching said barrier layer and said dielectric layer to define a contact opening extending through said barrier layer and said dielectric layer to expose at least a portion of said at least one active-device region of said semiconductor substrate; depositing an electrically conductive silicidable material over said barrier layer and into said contact opening wherein a portion of said electrically conductive silicidable material contacts said exposed at least one active-device region of the semiconductor substrate, said electrically conductive silicidable material being different from a material of the barrier layer; and annealing said electrically conductive silicidable material to said semiconductor substrate so as to form a silicide contact from said portion of electrically conductive silicidable material in contact with said at least one active-device region of said semiconductor substrate.
Claim 2
Independent Claim 162 words
A method of forming a contact interface, comprising: providing a semiconductor substrate having at least one active-device region; forming a dielectric layer over said semiconductor substrate; forming a barrier layer over said dielectric layer; etching said barrier layer and said dielectric layer to define a contact opening extending through said barrier layer and said dielectric layer to expose at least a portion of said at least one active-device region of said semiconductor substrate; depositing an electrically conductive silicidable material over said barrier layer and into said contact opening wherein a portion of said electrically conductive silicidable material contacts said exposed at least one active-device region of the semiconductor substrate, said electrically conductive silicidable material being different from a material of the barrier layer; and annealing said electrically conductive silicidable material to said semiconductor substrate so as to form a silicide contact from said portion of electrically conductive silicidable material in contact with said at least one active-device region of said semiconductor substrate.
Claim 3
Dependent Claim 27 words
The method of claim 1 , wherein said forming said dielectric layer over said semiconductor substrate comprises depositing a layer of TEOS dioxide over said semiconductor substrate.
Claim 4
Dependent Claim 27 words
The method of claim 1 , wherein said forming said barrier layer over said dielectric layer comprises depositing a layer of titanium nitride over said dielectric layer.
Claim 5
Dependent Claim 38 words
The method of claim 1 , wherein said depositing said eletrically conductive silicidable material over said barrier layer and into said contact opening comprises depositing a layer of cobalt over said barrier layer and into said contact opening.
Claim 6
Dependent Claim 27 words
The method of claim 1 , wherein said annealing is effected by heating said semiconductor substrate to a temperature of between about 400 and about 800° C.
Claim 7
Dependent Claim 17 words
The method of claim 5 , wherein said annealing temperature is between about 450 and 600° C.
Claim 8
Dependent Claim 18 words
The method of claim 1 , further including removing a non-reacted portion of said electrically conductive silicidable material.
Claim 9
Dependent Claim 26 words
The method of claim 7 , wherein said removing said non-reacted portion of said electrically conductive silicidable material is effected by application of an HPM solution.
Claim 10
Dependent Claim 19 words
The method of claim 1 , furher including removing said barrier layer after said annealing of said semiconductor substrate.
Claim 11
Dependent Claim 18 words
The method of claim 9 , wherein said removing layer is effected by application of an APM solution.
Claim 12
Independent Claim 152 words
A method of forming a DRAM chip, comprising: providing a semiconductor substrate having an active-device region; depositing a dielectric layer over said semiconductor substrate; forming a barrier layer over said dielectric layer; etching said barrier layer and said dielectric layer to define a contact opening extending through said barrier layer and said dielectric layer to expose at least a portion of said active-device region of said semiconductor substrate; depositing an electrically conductive silicidable material over said barrier layer and into said contact opening wherein a portion of said electrically conductive silicidable material contacts said exposed portion of said active-device region of the semiconductor substrate, said electrically conductive silicidable material being different from a material of the barrier layer, and annealing said electrically conductive silicidable material to said semiconductor substrate to form a silicide contact from said portion of electrically conductive silicidable material in contact with said active-device region of said semiconductor substrate.
Claim 13
Independent Claim 152 words
A method of forming a DRAM chip, comprising: providing a semiconductor substrate having an active-device region; depositing a dielectric layer over said semiconductor substrate; forming a barrier layer over said dielectric layer; etching said barrier layer and said dielectric layer to define a contact opening extending through said barrier layer and said dielectric layer to expose at least a portion of said active-device region of said semiconductor substrate; depositing an electrically conductive silicidable material over said barrier layer and into said contact opening wherein a portion of said electrically conductive silicidable material contacts said exposed portion of said active-device region of the semiconductor substrate, said electrically conductive silicidable material being different from a material of the barrier layer, and annealing said electrically conductive silicidable material to said semiconductor substrate to form a silicide contact from said portion of electrically conductive silicidable material in contact with said active-device region of said semiconductor substrate.
Claim 14
Independent Claim 125 words
A method of forming a contact interface, comprising: providing a semiconductor substrate having at least one contact projection; forming a first dielectric layer over said semiconductor substrate and said at least one contact projection; depositing a polysilicon layer over said first dielectric layer; depositing a barrier layer over said polysilicon layer; etching said barrier layer to expose said polysilicon layer over said at least one contact projection; depositing an electrically conductive silicidable material over said barrier layer and said exposed polysilicon layer, said electrically conductive silicidable material being different from a material of said barrier layer; and annealing said electrically conductive silicidable material to said semiconductor substrate to form a silicide contact from said exposed polysilicon layer in contact with said electrically conductive silicidable material.
Claim 15
Independent Claim 125 words
A method of forming a contact interface, comprising: providing a semiconductor substrate having at least one contact projection; forming a first dielectric layer over said semiconductor substrate and said at least one contact projection; depositing a polysilicon layer over said first dielectric layer; depositing a barrier layer over said polysilicon layer; etching said barrier layer to expose said polysilicon layer over said at least one contact projection; depositing an electrically conductive silicidable material over said barrier layer and said exposed polysilicon layer, said electrically conductive silicidable material being different from a material of said barrier layer; and annealing said electrically conductive silicidable material to said semiconductor substrate to form a silicide contact from said exposed polysilicon layer in contact with said electrically conductive silicidable material.
Claim 16
Dependent Claim 28 words
The method of claim 12 , wherein said forming said first dielectric layer over said semiconductor substrate comprises forming a layer of silicon dioxide over said semiconductor substrate.
Claim 17
Dependent Claim 27 words
The method of claim 12 , whermin said forming said barrier layer over said polysilicon layer comprises depositing a layer of titanium nitride ovcr. said polysilicon layer.
Claim 18
Dependent Claim 38 words
The method of claim 12 , wherein said depositing said ltrically conductive silicidable material over said baiier layer aind said exposed polysilicon layer comprises depositing a layer of cobalt over said barrier layer and said exposed polysilicon layer.
Claim 19
Dependent Claim 27 words
The method of claim 12 , wherein said annealing is effected by heating said semiconductor substrate to a temperature of between about 400° and about 800° C.
Claim 20
Dependent Claim 17 words
The method of claim 16 , wherein said annealing temperature is between about 450° and 600° C.
Claim 21
Independent Claim 19 words
The method, of clai 12 , further including removing a non-reacted portion of said cl aijl ucbie silicidable material.
Claim 22
Independent Claim 19 words
The method, of clai 12 , further including removing a non-reacted portion of said cl aijl ucbie silicidable material.
Claim 23
Dependent Claim 26 words
The method of claim 18 , wherein said removing said non-reacted portionl of said electrically conductive silicidable material is effected by application of an HPM solution.
Claim 24
Dependent Claim 19 words
The method of claim 12 , further including removing said barrier layer after said annealing of said semiconductor substrate.
Claim 25
Dependent Claim 20 words
The method of claim 20 , wherein said removing said barrier layer is effected by application of an APM solution.
Claim 26
Dependent Claim 21 words
The method of claim 12 , further including disposing a second dielectric layer between said polysilicon layer and said barrier layer.
Claim 27
Dependent Claim 35 words
The method of claim 22 , wherein said disposing said second dielectric layer between said polysilicon layer and said barrier layer comprises depositing a layer of TEOS between said polysilicon layer and said barrier layer.
Claim 28
Dependent Claim 36 words
The method of claim 22 , wherein said disposing said second dielectric layer between said polysilicon layer and said barrier layer comprises depositing a layer of silicon dioxide between said polysilicon layer and said barrier layer.
Claim 29
Dependent Claim 23 words
The method of claim 1 , wherein said forming said dielectric layer comprises forming said dielectric layer with a thickness of approximately 1,000Å.
Claim 30
Dependent Claim 29 words
The method of claim 7 , wherein said removing said non-reacted portion of said electrically silicidable material is effected without substantially removing reacted electrically silicidable material of said portion.
Claim 31
Dependent Claim 28 words
The method of claim 26 , wherein said. removing said non-reacted portion of said conductivc silicidable material is effected without substantially removing said material of said bsneer layer.
Claim 32
Dependent Claim 25 words
The method of claim 9 , whereic said removing said barrier layer is effected without substantially removing reacted electrcally conductive silicidable material of said portion.
Claim 33
Dependent Claim 20 words
The method of claim 28 , wherein said removing said barrier layer is effected without substantially removing said dielectric layer.
Claim 34
Dependent Claim 19 words
The method of claim 9 , wherein said removing said barrier layer comprises substantially completely removing said barrier layer.
Claim 35
Dependent Claim 39 words
The method of claim 1 ; wherein said fonling said barrier layer comprises preventing said ct it silicidable material from reacting with said semiconductor substrate through et least one of a void and an imperfection in said dielectric layer.
Claim 36
Dependent Claim 32 words
The method of claim 1 , wherein said forming said barrier layer comprises forming a layer comprising at least one of titanium nitride, tungsten nitride, tungsten silicon nitride, and titanium silicon nitride.
Claim 37
Dependent Claim 23 words
The method of claim 12 , wherein said forming said dielectric layer comprises forming said dielectric layer with a thickness of approximately 1,000Å.
Claim 38
Dependent Claim 26 words
The method of claim 18 , wherein said removing said non-reacted portion of said electrically silicidable material is effected without substantially removing reacted electrically silicidable material.
Claim 39
Dependent Claim 28 words
The method of claim 34 , wherein said removing said non-reacted portion of said electrically silicidable material is effected without substantially removing said material of said barrier layer.
Claim 40
Independent Claim 25 words
The method of clairn 20 , wherein said removing said barrier layer is effected without substantially removing reacted electrically conductive silicidable material of said portion.
Claim 41
Independent Claim 25 words
The method of clairn 20 , wherein said removing said barrier layer is effected without substantially removing reacted electrically conductive silicidable material of said portion.
Claim 42
Dependent Claim 20 words
The method of claim 36 , wherein said removing said barrier layer is effected without substantially removing said dielectric layer.
Claim 43
Dependent Claim 19 words
The method of claim 20 , wherein said removing said barrier layer comprises substantially completely removing said barrier layer.
Claim 44
Dependent Claim 38 words
The method of claim 12 , wherein said forming said barrier layer comprises preventing said electrically silicidablc material from reacting with said semiconductor substrate through at least one of a void and an imperfection in said dielectric layer.
Claim 45
Dependent Claim 32 words
The method of claim 12 , wherein said forming said barrier layer comprises forming a layer comprising at least one of titanium nitride, tungsten nitride, tungsten silicon nitride, and titanium silicon nitride.

References Cited (Backward Citations)

US4178605A Cited
US4305200A Cited
US4374700A Cited
US4570328A Cited
US4545116A Cited
US4470189A Cited
US4502209A Cited
US4593454A Cited
US4804636A Cited
US5371041A Cited
US5066615A Cited
US5444018A Cited
US5384285A Cited
US5612250A Cited
US5696017A Cited
US5510292A Cited
US5665641A Cited
US5718800A Cited
US5847463A Cited
US5981380A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-05-21 2004-11-20 2005-05-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-05-21 2008-11-20 2009-05-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-05-21 2012-11-20 2013-05-22 $7700.00 Window Closed / Lapsed

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