Patent US6235586B1 successfully refreshed from Google Patents.
US6235586B1
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Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications
Assignee: Monterey Research LLC
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Filing: 1999-07-13
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Granted: 2001-05-22
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Expires: 2019-07-13
Abstract
Abstract In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
Inventors
- 👤 Kenneth Wo-Wai Au
- 👤 Kent Kuohua Chang
- 👤 Hao Fang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:42
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30; H10B41/35
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
246 words
A method of forming a NAND type flash memory device, comprising: growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
Claim 2
Independent Claim
246 words
A method of forming a NAND type flash memory device, comprising: growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
Claim 3
Dependent Claim
22 words
The method of claim 1 , wherein the first oxide layer has a thickness from about 130 Å to about 170 Å.
Claim 4
Dependent Claim
24 words
The method of claim 1 , wherein the first in situ doped amorphous silicon layer comprises a phosphorus in situ doped amorphous silicon layer.
Claim 5
Dependent Claim
24 words
The method of claim 1 , wherein the first doped amorphous silicon layer has a thickness from about 600 Å to about 900 Å.
Claim 6
Dependent Claim
32 words
The method of claim 1 , wherein the dielectric layer comprises a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.
Claim 7
Dependent Claim
28 words
The method of claim 1 , wherein the second oxide layer in the flash memory cell area has a thickness from about 70 Å to about 110 Å.
Claim 8
Dependent Claim
25 words
The method of claim 1 , wherein the first and second oxide layers have a combined thickness from about 150 Å to about 190 Å.
Claim 9
Dependent Claim
33 words
The method of claim 1 , wherein the second doped amorphous silicon layer comprises a phosphorus in situ doped amorphous silicon layer having a thickness from about 1,000 Å to about 1,400 Å.
Claim 10
Independent Claim
294 words
A method of forming a flash memory cell and a select gate transistor of a NAND type flash memory device, comprising: growing a first oxide layer having a thickness from about 130 Å to about 170 Å over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first doped amorphous silicon layer having a thickness from about 500 Å to about 950 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; depositing a tungsten silicide layer over the second doped amorphous silicon layer using SiH 2 Cl 2 and WF 6 ; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, the second doped amorphous silicon layer, and the tungsten silicide layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, the second doped amorphous silicon layer, and the tungsten silicide layer.
Claim 11
Independent Claim
294 words
A method of forming a flash memory cell and a select gate transistor of a NAND type flash memory device, comprising: growing a first oxide layer having a thickness from about 130 Å to about 170 Å over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first doped amorphous silicon layer having a thickness from about 500 Å to about 950 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; depositing a tungsten silicide layer over the second doped amorphous silicon layer using SiH 2 Cl 2 and WF 6 ; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, the second doped amorphous silicon layer, and the tungsten silicide layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, the second doped amorphous silicon layer, and the tungsten silicide layer.
Claim 12
Dependent Claim
37 words
The method of claim 9 , wherein the first in situ doped amorphous silicon layer is deposited at a temperature from about 490° C. to about and a pressure from about 350 mTorr to about 600 mTorr.
Claim 13
Dependent Claim
23 words
The method of claim 9 , wherein the first in situ doped amorphous silicon layer comprises at least one of phosphorus and arsenic.
Claim 14
Dependent Claim
32 words
The method of claim 9 , wherein the first in situ doped amorphous silicon layer has a dopant concentration from about 1×10 16 ions/cm 3 to about 1×10 20 ions/cm 3 .
Claim 15
Dependent Claim
44 words
The method of claim 9 , wherein the dielectric layer has a thickness from about 110 Å to about 150 Å and comprises a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.
Claim 16
Dependent Claim
35 words
The method of claim 9 , wherein the tungsten silicide layer is deposited at a temperature from about 450° C. to about 650° C. and a pressure from about 70 Pa to about 120 Pa.
Claim 17
Dependent Claim
55 words
The method of claim 9 , wherein the tungsten silicide layer is deposited using a gas flow comprising from about 50 sccm to about 250 sccm SiH 2 Cl 2 and from about 2 sccm to about 10 sccm WF 6 and optionally from about 100 sccm to about 250 sccm of an inert gas.
Claim 18
Independent Claim
139 words
A method of forming a select gate transistor for a NAND type flash memory device, comprising: forming a first oxide layer having a thickness from about 130 Å to about 170 Å over at least a portion of a substrate; forming a second oxide layer over the first oxide layer to provide a gate oxide, the gate oxide having a thickness from about 150 Å to about 190 Å; and depositing an in situ doped amorphous silicon layer over the gate oxide at a temperature from about 450° C. to about 590° C. under a pressure from about 300 mTorr to about 700 mTorr, the in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å, and a dopant concentration from about 1×10 15 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 19
Independent Claim
139 words
A method of forming a select gate transistor for a NAND type flash memory device, comprising: forming a first oxide layer having a thickness from about 130 Å to about 170 Å over at least a portion of a substrate; forming a second oxide layer over the first oxide layer to provide a gate oxide, the gate oxide having a thickness from about 150 Å to about 190 Å; and depositing an in situ doped amorphous silicon layer over the gate oxide at a temperature from about 450° C. to about 590° C. under a pressure from about 300 mTorr to about 700 mTorr, the in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å, and a dopant concentration from about 1×10 15 ions/cm 3 to about 2×10 20 ions/cm 3 .
Claim 20
Dependent Claim
18 words
The method of claim 16 , wherein the first oxide layer is formed using a dry oxidation process.
Claim 21
Dependent Claim
21 words
The method of claim 16 , wherein the gate oxide has a thickness from about 160 Å to about 180 Å.
Claim 22
Dependent Claim
25 words
The method of claim 16 , wherein the in situ doped amorphous silicon layer having a thickness from about 600 Å to about 900 Å.
Claim 23
Dependent Claim
33 words
The method of claim 16 , wherein the in situ doped amorphous silicon layer has a phosphorus dopant concentration is from about 1×10 17 ions/cm 3 to about 5×10 19 ions/cm 3 .
References Cited (Backward Citations)
US5824583A
Cited
US5424232A
Cited
US5668034A
Cited
US5471070A
Cited
US5643633A
Cited
US5637520A
Cited
EP0612108A1
Cited
US5493140A
Cited
US5597749A
Cited
US5511020A
Cited
EP0663695A2
Cited
US5910016A
Cited
US5661053A
Cited
US5830794A
Cited
US5891794A
Cited
US5981340A
Cited
US6023085A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-21 | 2004-11-20 | 2005-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-21 | 2008-11-20 | 2009-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-21 | 2012-11-20 | 2013-05-22 | $7700.00 | Window Closed / Lapsed |