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US5910016A Expired / Lapsed US ⏱️ 0.0 years remaining

Scalable EPROM array

Assignee: STMicroelectronics lnc USA
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Filing: 1997-02-25
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Granted: 1999-06-08
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Expires: 2017-02-25
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Abstract

Abstract An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.

Inventors

  • 👤 Reza Kazerounian
  • 👤 Rustom F. Irani
  • 👤 Boaz Eitan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 07:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; H; H10; H10B; H10B41/00; H10B41/30; H10B69/00

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 107 words
For an alternating metal virtual ground EPROM array having EPROM areas and control areas, each control area comprising select transistors and isolation units located between neighboring ones of the select transistors, the method of manufacturing the isolation units comprising the steps of: creating areas of thick oxide and areas of thin oxide in said control areas; with a mask, laying down strips of first polysilicon over at least a part of each of said thick and thin oxide portions; and etching said thick and thin oxide portions in accordance with said mask, thereby to align said thick and thin oxide portions with said strips of first polysilicon.
Claim 2
Dependent Claim 107 words
For an alternating metal virtual ground EPROM array having EPROM areas and control areas, each control area comprising select transistors and isolation units located between neighboring ones of the select transistors, the method of manufacturing the isolation units comprising the steps of: creating areas of thick oxide and areas of thin oxide in said control areas; with a mask, laying down strips of first polysilicon over at least a part of each of said thick and thin oxide portions; and etching said thick and thin oxide portions in accordance with said mask, thereby to align said thick and thin oxide portions with said strips of first polysilicon.
Claim 3
Dependent Claim 19 words
A method according to claim 1 and wherein said step of etching is performed with a 20:1 etch process.
Claim 4
Dependent Claim 18 words
A method according to claim 1 and wherein said thick oxide portion has a thickness of 1000-2000 Å.
Claim 5
Dependent Claim 27 words
A method according to claim 1 and including, after the step of etching, the step of laying down a spacer next to said strips of first polysilicon.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-06-07 2002-12-07 2003-06-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-06-07 2006-12-07 2007-06-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-06-07 2010-12-07 2011-06-08 $7700.00 Window Closed / Lapsed

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