Pseudo-nonvolatile memory incorporating data refresh operation

Claim 2

A pseudo-nonvolatile memory (PNVM) system comprising: a transistor comprising a substrate having a source region and a drain region spaced apart from the source region, a charge retaining region overlying the substrate and spaced apart therefrom, a control gate overlying the charge retaining region and spaced apart therefrom, a direct tunneling dielectric having a thickness less than a thickness of a Fowler-Nordheim tunneling dielectric, the direct tunneling dielectric juxtaposed with the charge retaining region, whereby transfer of charge occurs through the direct tunneling dielectric to the charge retaining region; and a refresher circuit coupled to the transistor, wherein the refresher circuit periodically refreshes the charge stored in the charge retaining region.

Claim 3

The PNVM system of claim 1, further comprising a programming circuit connected to the transistor, said programming circuit having means for applying a write voltage across said control gate and said substrate to store a charge in said charge retaining region and means for applying an erase voltage across said control gate and said substrate to remove a charge from said charge retaining region.

Claim 4

The PNVM system of claim 2, wherein the programming circuit limits the voltage applied across said direct tunneling dielectric to less than 5 volts.

Claim 5

The PNVM system of claim 2, wherein the application of the write voltage causes the charge to be stored in said charge retaining region in less than 1 micro-second.

Claim 6

The PNVM system of claim 2, wherein the application of the erase voltage causes the charge to be removed from said charge retaining region in less than 100 micro-seconds.

Claim 7

The PNVM system of claim 1, wherein said refresher circuit comprises an input terminal connectable to receive a refresh request signal used to initiate operation of the refresher circuit.

Claim 8

The PNVM system of claim 6, wherein said transistor is located on a chip, and said refresh request signal is generated on said chip.

Claim 9

The PNVM system of claim 6, wherein said transistor is located on a chip, and said refresh request signal is generated off of said chip.

Claim 10

The PNVM system of claim 6, wherein said refresher circuit comprises, a bitline coupled to said substrate; a read voltage supply coupled to said control gate, wherein said read voltage supply selectively applies a read voltage to said control gate, wherein a signal representative of the charge on said charge retaining region is read out onto said bitline when said read voltage is applied to said control gate; an inverter circuit coupled to said bitline, wherein said inverter circuit amplifies and inverts said signal to create a programming signal which is returned to said transistor on said bitline; and a programming voltage supply coupled to said control gate, wherein said programming voltage supply selectively applies a programming voltage to said control gate during the time that said programming signal is returned to said transistor, whereby said charge stored in said charge retaining region is refreshed.

Claim 11

The PNVM system of claim 9, wherein said bitline is connected to said source of said transistor.

Claim 12

The PNVM system of claim 9, wherein said bitline is connected to said drain of said transistor.

Claim 13

The PNVM system of claim 6, wherein said refresher circuit comprises, a first bitline coupled to said substrate; a read voltage supply coupled to said control gate, said read voltage supply selectively applying a read voltage to said control gate, wherein a signal representative of the charge on said charge retaining region is read out onto said first bitline when said read voltage is applied to said control gate; an inverter circuit coupled to said first bitline, wherein said inverter circuit amplifies and inverts said signal to create a programming signal; a second bitline coupled to said inverter circuit, said second bitline receiving said programming signal; a pre-erased transistor having a substrate coupled to said second bitline, wherein said signal is applied to said substrate of said pre-erased transistor; and a programming voltage supply coupled to a control gate of said pre-erased transistor, said programming voltage supply selectively applying a programming voltage to the control gate of said pre-erased transistor, wherein said programming voltage is applied to said control gate of said pre-erased transistor during the time that said programming signal is applied to said substrate of said pre-erased transistor, whereby said charge is refreshed in said pre-erased transistor.

Claim 14

The PNVM system of claim 12, wherein said refresher circuit further comprises, an addressing circuit which assigns an address corresponding to said transistor to said pre-erased transistor after the charge is refreshed in said pre-erased transistor.

Claim 15

The PNVM system of claim 12, wherein said refresher circuit further comprises, a circuit which erases the charge in said charge retaining region of said transistor after the charge is refreshed in said pre-erased transistor; and means for assigning an unused address to said transistor.

Claim 16

The PNVM system of claim 1, wherein said refresher circuit comprises a back-up battery and a controller circuit.

Claim 17

The PNVM system of claim 15, wherein said back-up battery is rechargeable.

Claim 18

The PNVM system of claim 15 wherein said controller circuit is coupled to said back-up battery and said controller circuit generates a refresh request signal to initiate the refreshing of the charge stored in the charge retaining region.

Claim 19

The PNVM system of claim 15, wherein said controller circuit comprises a timer which causes the controller circuit to generate refresh request signals at a preselected frequency, wherein each of said refresh request signals initiates the refreshing of the charge stored in the charge retaining region.

Claim 20

The PNVM system of claim 15, wherein said controller circuit comprises: a reference transistor; means for monitoring a charge on said reference transistor; and means for generating a refresh request signal when said charge on said reference transistor drops below a preselected level, wherein said refresh request signal initiates the refreshing of the charge stored in the charge retaining region.

Claim 21

The PNVM system of claim 15, wherein said controller circuit comprises a power switch that connects the transistor to the back-up battery.

Claim 22

The PNVM system of claim 20, wherein said power switch connects the transistor to the back-up battery only if said transistor is not coupled to an external power supply.

Claim 23

The PNVM system of claim 15, wherein said controller circuit comprises a charge pump coupled to said back-up battery, said charge pump boosting the magnitude of the voltage of said back-up battery to create a programming voltage, wherein said programming voltage is used to refresh the charge on said transistor.

Claim 24

The PNVM system of claim 22, wherein said charge pump is located on a chip containing said transistor.

Claim 25

The PNVM system of claim 22, wherein said charge pump is located off a chip containing said transistor.

Claim 26

The PNVM system of claim 22, wherein said charge pump is disabled when an external power supply is coupled to said transistor.

Claim 27

The PNVM system of claim 1, wherein the thickness of said direct tunneling dielectric is between 0.5 nanometers and 5 nanometers.

Claim 28

The PNVM system of claim 26, wherein said direct tunneling dielectric comprises an oxide, a poly-oxide, a nitride or an oxy-nitride.

Claim 29

The PNVM system of claim 1, wherein said charge retaining region comprises an insulating dielectric.

Claim 30

The PNVM system of claim 28, wherein said insulating dielectric comprises a nitride.

Claim 31

The PNVM system of claim 1, wherein said charge retaining region comprises an interface between insulating dielectrics.

Claim 32

The transistor of claim 1, wherein said charge retaining region comprises a floating gate.

Claim 33

The transistor of claim 31, wherein said floating gate comprises a metal.

Claim 34

The transistor of claim 32, wherein said metal comprises platinum.

Claim 35

The PNVM system of claim 1, wherein said direct tunneling dielectric is positioned between said substrate and said charge retaining region.

Claim 36

The PNVM system of claim 1, wherein said direct tunneling dielectric is positioned between said control gate and said charge retaining region.

Claim 37

The PNVM system of claim 1, wherein said direct tunneling dielectric is positioned at an edge of said charge retaining region.

Claim 38

The PNVM system of claim 1, wherein the charge is retained by said charge retaining region for a data retention period substantially less than ten years.

Claim 39

The PNVM system of claim 1, wherein the charge is retained by said charge retaining region for a data retention period less than 1 month.

Claim 40

The PNVM system of claim 1 wherein said charge retaining region overlies said source and said drain.

Claim 41

The PNVM system of claim 1, wherein said charge retaining region overlies said drain but not said source.

Claim 42

The PNVM system of claim 1, wherein said charge retaining region overlies said source but not said drain.

Claim 43

The PNVM system of claim 1, wherein said charge retaining region does not overlap either said source or said drain.

Claim 44

The PNVM system of claim 1, wherein the thickness of said direct tunneling dielectric is less than 8 nanometers.