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US5140552A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device having a volatile memory device and a non-volatile memory device

Assignee: Sharp Corp
•
Filing: 1991-04-18
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Granted: 1992-08-18
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Expires: 2011-04-18
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Abstract

Abstract A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch circuit for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated. The EEPROM consists of a floating gate and a control gate, and the mode switch circuit consists of a MOS transistor having a control gate integrally formed with the control gate of the EEPROM.

Inventors

  • 👤 Yoshimitsu Yamauchi
  • 👤 Kenichi Tanaka
  • 👤 Keizo Sakiyama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 15:03
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/005; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C14/00; G11C16/00; G11C16/02; G11C16/04

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 178 words
In a semiconductor memory device comprising: a volatile memory means; a non-volatile memory means; a mode switch means for selecting either mode of a volatile memory mode in which said memory device functions as a volatile memory device and a non-volatile memory mode in which said memory device functions as a non-volatile memory device; and a transfer means for transferring data between said volatile memory means and said non-volatile memory means in accordance with the mode selected by said switch means, the improvement existing in that said volatile memory means consists of one transistor and one capacitor, and one of the terminals of said capacitor is electrically isolated from said non-volatile memory means and electrically coupled to a terminal to which one of a plurality of predetermined voltages is applied and said non-volatile memory means comprises a first MOS transistor having a floating gate and a control gate, and said mode switch means comprises a second MOS transistor, said control gate of said first MOS transistor and the control gate of said second MOS transistor being formed integrally.
Claim 2
Dependent Claim 178 words
In a semiconductor memory device comprising: a volatile memory means; a non-volatile memory means; a mode switch means for selecting either mode of a volatile memory mode in which said memory device functions as a volatile memory device and a non-volatile memory mode in which said memory device functions as a non-volatile memory device; and a transfer means for transferring data between said volatile memory means and said non-volatile memory means in accordance with the mode selected by said switch means, the improvement existing in that said volatile memory means consists of one transistor and one capacitor, and one of the terminals of said capacitor is electrically isolated from said non-volatile memory means and electrically coupled to a terminal to which one of a plurality of predetermined voltages is applied and said non-volatile memory means comprises a first MOS transistor having a floating gate and a control gate, and said mode switch means comprises a second MOS transistor, said control gate of said first MOS transistor and the control gate of said second MOS transistor being formed integrally.

References Cited (Backward Citations)

US3911464A Cited
US4271487A Cited
US4354255A Cited
US4786954A Cited
US4721987A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-08-18 1996-02-17 1996-08-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-08-18 2000-02-17 2000-08-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-08-18 2004-02-17 2004-08-18 $7700.00 Window Closed / Lapsed

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