Patent US6223148B1 successfully refreshed from Google Patents.
US6223148B1
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Logic analysis system for logic emulation systems
Assignee: Mentor Graphics Corp
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Filing: 1998-08-14
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Granted: 2001-04-24
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Expires: 2018-08-14
Abstract
Abstract A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased. Each probe of the logic analyzer can now receive multiple time-division multiplex logic values for each emulation clock cycle thus, increasing the width of logic analysis that can be performed on a particular emulation system with the conventional logic analyzers.
Inventors
- 👤 Kem Stewart
- 👤 Charles W. Selvidge
- 👤 Kenneth Crouch
- 👤 Marina Wong
- 👤 Mark Seneski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G06; G06F; G06F11/00; G06F11/22; G06F11/25; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
97 words
A logic analysis system for a digital logic emulation system configured to model a digital system and operating in response to at least one emulation clock signal, the logic analysis system comprising: a clock signal generator for generating a multiplexing clock signal; a configurable multiplexing subsystem for transmitting logic values of logic signals from the digital logic emulation system to a logic analyzer, the multiplexing subsystem multiplexing multiple logic values on channels of the logic analyzer for cycles of the emulation clock in response to the multiplexing clock signal; and a controller which configures the multiplexing subsystem.
Claim 2
Dependent Claim
97 words
A logic analysis system for a digital logic emulation system configured to model a digital system and operating in response to at least one emulation clock signal, the logic analysis system comprising: a clock signal generator for generating a multiplexing clock signal; a configurable multiplexing subsystem for transmitting logic values of logic signals from the digital logic emulation system to a logic analyzer, the multiplexing subsystem multiplexing multiple logic values on channels of the logic analyzer for cycles of the emulation clock in response to the multiplexing clock signal; and a controller which configures the multiplexing subsystem.
Claim 3
Dependent Claim
31 words
A system as described in claim 1 , wherein the multiplexing clock signal from the clock generator has a frequency that is higher than each one of the emulation clock signals.
Claim 4
Dependent Claim
25 words
A system as described in claim 1 , wherein the multiplexing subsystem transmits the multiplexing clock signal to the logic analyzer as a strobe signal.
Claim 5
Dependent Claim
28 words
A system as described in claim 1 , wherein the multiplexing subsystem is implemented in a reconfigurable logic system in which the digital logic emulation system is implemented.
Claim 6
Dependent Claim
30 words
A system as described in claim 1 , wherein the multiplexing subsystem transmits tag signals to the logic analyzer to identify the logic values being transmitted to the logic analyzer.
Claim 7
Dependent Claim
52 words
A system as described in claim 1 , wherein the multiplexing subsystem comprises: a multiplexor circuit for receiving and then transmitting the logic values to the logic analyzer; and a controller for controlling the multiplexor circuit to sample the logic signals to obtain the logic values and to transmit the logic values.
Claim 8
Dependent Claim
68 words
A logic emulation system including reconfigurable logic devices and an interconnect for transmitting logic signals between the logic devices, and being configured to comprise: a digital logic emulation portion for modeling a digital system operating in response to at least one emulation clock signal; and a logic analysis multiplexing portion for transmitting logic values of logic signals from the digital logic emulation portion to a logic analysis device.
Claim 9
Dependent Claim
68 words
A logic emulation system including reconfigurable logic devices and an interconnect for transmitting logic signals between the logic devices, and being configured to comprise: a digital logic emulation portion for modeling a digital system operating in response to at least one emulation clock signal; and a logic analysis multiplexing portion for transmitting logic values of logic signals from the digital logic emulation portion to a logic analysis device.
Claim 10
Dependent Claim
32 words
A system as described in claim 7 , wherein the logic analysis multiplexing portion transmits multiple logic values on channels of the logic analysis device for cycles of the emulation clock signal.
Claim 11
Dependent Claim
29 words
A system as described in claim 7 , further comprising a clock signal generator for generating a multiplexing clock signal having a higher frequency than the emulation clock signal.
Claim 12
Dependent Claim
31 words
A system as described in claim 9 , wherein the logic analysis multiplexing portion multiplexes the logic values transmitted to the logic analysis device in response to the multiplexing clock signal.
Claim 13
Dependent Claim
15 words
A system as described in claim 7 , wherein the reconfigurable logic devices comprise FPGA's.
Claim 14
Independent Claim
89 words
A method for sampling digital signals from a digital logic emulation system configured to operate in a digital system having an emulation clock signal, the method comprising: configuring an emulated circuit and a logic analysis multiplexor; sampling selected digital signals within the emulation system; collecting digital signal values associated with the sampled digital signals for cycles of the emulation clock signal; and in the configured logic analysis multiplexor, multiplexing multiple ones of the digital signal values to a logic analysis device in individual cycles of the emulation clock signal.
Claim 15
Independent Claim
89 words
A method for sampling digital signals from a digital logic emulation system configured to operate in a digital system having an emulation clock signal, the method comprising: configuring an emulated circuit and a logic analysis multiplexor; sampling selected digital signals within the emulation system; collecting digital signal values associated with the sampled digital signals for cycles of the emulation clock signal; and in the configured logic analysis multiplexor, multiplexing multiple ones of the digital signal values to a logic analysis device in individual cycles of the emulation clock signal.
Claim 16
Dependent Claim
34 words
A method as described in claim 12 , further comprising: generating a multiplexing clock signal; and multiplexing of the digital signal values to the logic analysis device in response to the multiplexing clock signal.
Claim 17
Dependent Claim
33 words
A method as described in claim 13 , further comprising: transmitting the multiplexing clock signal to the logic analysis device; and triggering the logic analysis device in response to the multiplexing clock signal.
Claim 18
Dependent Claim
20 words
A method as described in claim 12 , further comprising demultiplexing the digital signal values received from the emulation system.
Claim 19
Dependent Claim
22 words
A method as described in claim 15 , further comprising displaying the demultiplexed signal values in association with the emulation clock signal.
Claim 20
Dependent Claim
32 words
A method as described in claim 12 , further comprising multiplexing of the digital signal values to the logic analysis device in response to a virtual clock signal of the emulation system.
Claim 21
Dependent Claim
31 words
A method as described in claim 12 , further comprising transmitting tag signals to the logic analysis device to identify the digital signal values being transmitted to the logic analysis device.
Claim 22
Dependent Claim
34 words
A method as claimed in claim 18 , further comprising demultiplexing the logic values in response to the tag signals and aligning the logic values to correspond to cycles of the emulation clock signal.
Claim 23
Dependent Claim
25 words
A method as claimed in claim 18 , further comprising triggering the logic analysis device at least in part in response to the tag signals.
Claim 24
Dependent Claim
31 words
A method as described in claim 12 , wherein the step of sampling selected digital signals comprises sampling digital signals generated in programmable logic devices of the digital logic emulation system.
Claim 25
Independent Claim
84 words
A method for configuring a logic emulation system including reconfigurable logic devices and an interconnect for transmitting logic signals between the logic devices, the method comprising: programming the logic emulation system to have a digital logic emulation portion for modeling a digital system operating in response to at least one emulation clock signal; and programming the logic emulation system to have a logic analysis multiplexing portion for transmitting logic values of logic signals from the digital logic emulation portion to a logic analysis device.
Claim 26
Independent Claim
84 words
A method for configuring a logic emulation system including reconfigurable logic devices and an interconnect for transmitting logic signals between the logic devices, the method comprising: programming the logic emulation system to have a digital logic emulation portion for modeling a digital system operating in response to at least one emulation clock signal; and programming the logic emulation system to have a logic analysis multiplexing portion for transmitting logic values of logic signals from the digital logic emulation portion to a logic analysis device.
Claim 27
Dependent Claim
35 words
A method as described in claim 22 , further comprising programming the logic emulation system to multiplex multiple logic values on channels of the logic analysis device for every cycle of the emulation clock signal.
Claim 28
Dependent Claim
27 words
A system as described in claim 23 , where the digital logic emulation system comprises a plurality of programmable logic chips and an interconnect connecting the chips.
Claim 29
Dependent Claim
36 words
A method as described in claim 22 , wherein the step of programming the logic emulation system comprises programming reconfigurable logic devices within the logic emulation system in response to operating parameters of the digital system.
Claim 30
Dependent Claim
122 words
A digital logic analysis system, comprising: a target system for generating at least one target system clock signal and data signals; a programmable emulation system for executing a logic design being responsive to the target system clock signal and the data signals and generating data signals to the target system, the emulation system including a clock signal generator for generating a multiplexing clock signal; a logic analysis device connected to the emulation system for sampling logic signals within the emulation system; a configuring device for programming the emulation system to execute the logic design and multiplex logic values of the logic signals to the logic analyzer for every cycle of the target system clock signal in response to the multiplexing clock signal.
Claim 31
Dependent Claim
122 words
A digital logic analysis system, comprising: a target system for generating at least one target system clock signal and data signals; a programmable emulation system for executing a logic design being responsive to the target system clock signal and the data signals and generating data signals to the target system, the emulation system including a clock signal generator for generating a multiplexing clock signal; a logic analysis device connected to the emulation system for sampling logic signals within the emulation system; a configuring device for programming the emulation system to execute the logic design and multiplex logic values of the logic signals to the logic analyzer for every cycle of the target system clock signal in response to the multiplexing clock signal.
Claim 32
Dependent Claim
121 words
A logic analysis system for a digital logic emulation system configured to model a digital system and operating in response to at least two emulation clock signals, the logic analysis system comprising: a clock signal generator associated with each emulation clock signal for generating a multiplexing clock signal in response to the corresponding emulation clock signal; a configurable multiplexing subsystem associated with each clock signal generator for transmitting logic values of logic signals from the digital logic emulation system to a logic analyzer, the multiplexing subsystem multiplexing multiple logic values on each channel of the logic analyzer for every cycle of the corresponding emulation clock in response to the corresponding multiplexing clock signal; and a controller which configures the multiplexing subsystem.
Claim 33
Dependent Claim
121 words
A logic analysis system for a digital logic emulation system configured to model a digital system and operating in response to at least two emulation clock signals, the logic analysis system comprising: a clock signal generator associated with each emulation clock signal for generating a multiplexing clock signal in response to the corresponding emulation clock signal; a configurable multiplexing subsystem associated with each clock signal generator for transmitting logic values of logic signals from the digital logic emulation system to a logic analyzer, the multiplexing subsystem multiplexing multiple logic values on each channel of the logic analyzer for every cycle of the corresponding emulation clock in response to the corresponding multiplexing clock signal; and a controller which configures the multiplexing subsystem.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-04-23 | 2004-10-23 | 2005-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-04-23 | 2008-10-23 | 2009-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-04-23 | 2012-10-23 | 2013-04-24 | $7700.00 | Window Closed / Lapsed |