Data processor and method for providing show cycles on a fast multiplexed bus

Claim 2

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of control signals, the plurality of address values, and the plurality of data values, the system integration circuit generating a first control signal enabling the data processor to execute a show cycle, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is executing the show cycle, the first predetermined format including a first one of the plurality of data values which is associated with a first address value and is accessed during a first bus cycle, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during a second cycle in which a second one of the plurality of address values is provided to the multiplexed bus.

Claim 3

The data processor of claim 1 wherein the system integration circuit is coupled to a pipelined development system.

Claim 4

The data processor of claim 1 wherein the system integration circuit comprises: interface means coupled to the central processing unit for receiving the first one of the plurality of control signals, the plurality of address values, and the plurality of data values; and a bus control circuit coupled to the interface means for receiving the first one of the plurality of control signals, a plurality of address values, and a plurality of data values, the bus control circuit providing the plurality of address values and the plurality of data values in the first predetermined format.

Claim 5

The data processor of claim 3 wherein the system integration circuit comprises: a state machine for providing a plurality of state signals to control operation of the system integration circuit when the data processor is executing the show cycle, the state machine being coupled to the interface means for receiving the first one of the plurality of control signals.

Claim 6

The data processor of claim 4 wherein the bus control circuit comprises: a timing control circuit coupled to the interface means for receiving the first one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the timing control circuit providing a plurality of timing signals; a delay circuit coupled to the interface means for receiving the first one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the delay circuit providing a delay signal to indicate a timing delay operation; a data register for selectively storing each of the plurality of data values; an address register for selectively storing each of the plurality of address values; and a multiplexer for multiplexing each of the plurality of the data values with each of the plurality of address values to provide the plurality of address values and the plurality of data values in the first predetermined format, the multiplexer being coupled to the address register for receiving the plurality of address values, being coupled to the data register for receiving the plurality of data values, being coupled to the delay circuit for receiving the delay signal, and being coupled to the timing control circuit for receiving the plurality of timing signals.

Claim 7

The data processor of claim 1 wherein the second bus cycle is consecutive in time to the first bus cycle.

Claim 8

The data processor of claim 1 wherein the first one of the plurality of data values is accessed during one of a read operation or a write operation.

Claim 9

The data processor of claim 1 wherein the first one of the plurality of address values is accessed during one of a read and a write operation.

Claim 12

The method of claim 9 further comprising the steps of: coupling an interface circuit to the central processing unit for receiving the first one of the plurality of control signals, the plurality of address values, and the plurality of data values; coupling a state machine to the interface circuit for receiving the first one of the plurality of control signals, the state machine providing a plurality of state signals to control operation of the system integration circuit when the data processor is executing the show cycle; coupling a timing control circuit to the interface circuit for receiving the first one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the timing control circuit providing a plurality of timing signals; coupling a delay circuit coupled to the interface circuit for receiving the first one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the delay circuit providing a delay signal to indicate a timing delay operation; enabling a data register to selectively store each of the plurality of data values; enabling an address register to selectively store each of the plurality of address values; and providing a multiplexer for multiplexing each of the plurality of the data values with each of the plurality of address values to provide the plurality of address values and the plurality of data values in the first predetermined format, the multiplexer being coupled to the address register for receiving the plurality of address values, being coupled to the data register for receiving the plurality of data values, being coupled to the delay circuit for receiving the delay signal, and being coupled to the timing control circuit for receiving the plurality of timing signals.

Claim 13

The method of claim 9 wherein the second bus cycle is consecutive in time to the first bus cycle.

Claim 14

The method of claim 9 wherein the first one of the plurality of data values is accessed during one of a read operation and a write operation.

Claim 15

The method of claim 9 wherein the first one of the plurality of address values is accessed during one of a read and a write operation.

Claim 18

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of address values, the plurality of data values, and the plurality of control values, the system integration circuit generating a first one of the plurality of control signals to indicate the data processor is operating in an emulation mode and generating a second one of the plurality of control signals to indicate when the data processor is executing a show cycle, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is operating in a first mode of operation and the second one of the plurality of control signals enable the data processor to execute the show cycle, the first predetermined format providing a first one of the plurality of data values which is associated with a first one of the plurality of addresses and which is accessed during a first bus cycle, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during a first bus cycle and during a second bus cycle in which a second one of the plurality of address values is provided to the multiplexed bus, the system integration circuit also communicating a second one of the plurality of data values which is associated with the second one of the plurality of address values to the multiplexed bus.

Claim 19

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of address values, the plurality of data values, and the plurality of control values, the system integration circuit generating a first one of the plurality of control signals to indicate the data processor is operating in an emulation mode and generating a second one of the plurality of control signals to indicate when the data processor is executing a show cycle, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is operating in a first mode of operation and the second one of the plurality of control signals enable the data processor to execute the show cycle, the first predetermined format providing a first one of the plurality of data values which is associated with a first one of the plurality of addresses and which is accessed during a first bus cycle, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during a first bus cycle and during a second bus cycle in which a second one of the plurality of address values is provided to the multiplexed bus, the system integration circuit also communicating a second one of the plurality of data values which is associated with the second one of the plurality of address values to the multiplexed bus.

Claim 20

The data processor of claim 15 wherein the system integration circuit is coupled to an emulation system.

Claim 21

The data processor of claim 16 wherein the system integration circuit comprises: a state machine for providing a plurality of state signals to control operation of the system integration circuit when the data processor is executing the show cycle, the state machine being coupled to the interface means for receiving the first one of the plurality of control signals.

Claim 22

The data processor of claim 17 wherein the bus control circuit comprises: a timing control circuit coupled to the interface means for receiving the first one of the plurality of control signals and the second one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the timing control circuit providing a plurality of timing signals; a delay circuit coupled to the interface means for receiving the first one of the plurality of control signals and the second one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the delay circuit providing a delay signal to indicate a timing delay operation; a data register for selectively storing each of the plurality of data values; an address register for selectively storing each of the plurality of address values; and a multiplexer for multiplexing each of the plurality of the data values with each of the plurality of address values to provide to provide the plurality of address values and the plurality of data values in the first predetermined format, the multiplexer being coupled to the address register for receiving the plurality of address values, being coupled to the data register for receiving the plurality of data values, being coupled to the delay circuit for receiving the delay signal, and being coupled to the timing control circuit for receiving the plurality of timing signals.

Claim 23

The data processor of claim 15 wherein the system integration circuit comprises: interface means coupled to the central processing unit for receiving the first one of the plurality of control signals and the second one of the plurality of control signals, the plurality of address values, the plurality of data values, and the plurality of control signals; and a bus control circuit coupled to the interface means for receiving the first one of the plurality of control signals and the second one of the plurality of control signals, a plurality of address values, and a plurality of data values, the bus control circuit providing the plurality of address values and the plurality of data values in the first predetermined format.

Claim 24

The data processor of claim 15 wherein the second bus cycle is consecutive in time to the firs t bus cycle.

Claim 25

The data processor of claim 15 wherein the first one of the plurality of data values is accessed during a write operation and the second one of the plurality of data values is accessed during one of a read operation and a write operation.

Claim 26

The data processor of claim 15 wherein the first one of the plurality of address values is accessed during a write operation and the second one of the plurality of address values is accessed during one of a read or a write operation.

Claim 29

The method of claim 23 further comprising the steps of: enabling an interface circuit to receive the first one of the plurality of control signals and the second one of the plurality of control signals, the plurality of address values, and the plurality of data values; coupling a state machine to the interface circuit for receiving the first one of the plurality of control signals, the state providing a plurality of state signals to control operation of the system integration circuit when the data processor is executing the show cycle; coupling a timing control circuit to the interface circuit for receiving the first one of the plurality of control signals and the second one of the plurality of control signals and coupled to the state machine for receiving the plurality of state signals, the timing control circuit providing a plurality of timing signals; coupling a delay circuit to the interface circuit for receiving the first one of the plurality of control signals and the second one of the plurality of control signals and coupling the delay circuit to the state machine for receiving the plurality of state signals, the delay circuit providing a delay signal to indicate a timing delay operation; enabling a data register to selectively store each of the plurality of data values; enabling an address register to selectively store each of the plurality of address values; and providing a multiplexer for multiplexing each of the plurality of the data values with each of the plurality of address values to provide the plurality of address values and the plurality of data values in the first predetermined format, the multiplexer being coupled to the address register for receiving the plurality of address values, being coupled to the data register for receiving the plurality of data values, being coupled to the delay circuit for receiving the delay signal, and being coupled to the timing control circuit for receiving the plurality of timing signals.

Claim 30

The method of claim 23 wherein the second bus cycle is consecutive in time to the first bus cycle.

Claim 31

The method of claim 23 wherein the first one of the plurality of data values is accessed during a write operation and the second one of the plurality of data values is accessed during one of a read operation and a write operation.

Claim 32

The method of claim 23 wherein the first one of the plurality of address values is accessed during a read operation and the second one of the plurality of address values is accessed during a read operation and a write operation.

Claim 35

The method of claim 28 further comprising the steps of: enabling the system integration circuit to read a third data value at a third address location from the internal memory during a third bus cycle; enabling the system integration circuit to provide the third address location externally via the multiplexed bus during the third bus cycle; enabling the system integration circuit to provide the second data value externally via the multiplexed bus after the third address location is externally provided during the third bus cycle; and enabling the system integration circuit to provide the third data value externally via the multiplexed bus after the second data value is externally provided during the third bus cycle.

Claim 36

The method of claim 28 further comprising the steps of: enabling the system integration circuit to write a third data value to a third address location from the internal memory during a third bus cycle; enabling the system integration circuit to provide the third address location externally via the multiplexed bus during the third bus cycle; enabling the system integration circuit to provide the second data value externally via the multiplexed bus after the third address location is externally provided during the third bus cycle; and enabling the system integration circuit to provide tile third data value externally via the multiplexed bus after the second data value is externally provided during the third bus cycle.

Claim 37

The method of claim 28 wherein the first bus cycle is a read cycle and the second bus cycle is a write cycle.

Claim 38

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of address values, the plurality of data values, and the plurality of control values, the system integration circuit generating a first one of the plurality of control signals to indicate the data processor is operating in an emulation mode, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is operating in a first mode of operation, the first predetermined format providing a first one of the plurality of data values which is associated with a first one of the plurality of addresses and which is accessed during a first bus cycle, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during the first bus cycle and a second bus cycle in which a second one of the plurality of address values is provided to the multiplexed bus, the system integration circuit also communicating a second one of the plurality of data values which is associated with the second one of the plurality of address values to the multiplexed bus.

Claim 39

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of address values, the plurality of data values, and the plurality of control values, the system integration circuit generating a first one of the plurality of control signals to indicate the data processor is operating in an emulation mode, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is operating in a first mode of operation, the first predetermined format providing a first one of the plurality of data values which is associated with a first one of the plurality of addresses and which is accessed during a first bus cycle, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during the first bus cycle and a second bus cycle in which a second one of the plurality of address values is provided to the multiplexed bus, the system integration circuit also communicating a second one of the plurality of data values which is associated with the second one of the plurality of address values to the multiplexed bus.

Claim 40

The data processor of claim 32 wherein the system integration circuit generates a second one of the plurality of control signals to indicate when the data processor is executing a show cycle and the system integration circuit provides the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is operating in a first mode of operation and the second one of the plurality of control signals enable the data processor to execute the show cycle.

Claim 41

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of control signals, the plurality of address values, and the plurality of data values, the system integration circuit generating a first control signal enabling the data processor to execute a show cycle, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is executing the show cycle, the first predetermined format including a first one of the plurality of data values which is associated with a first address value and is accessed during a first bus cycles, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during a second cycle in which a second one of the plurality of address values is provided to the multiplexed bus; wherein the system integration circuit comprises: interface means coupled to the central processing unit for receiving the first one of the plurality of control signals, the plurality of address values, and the plurality of data values; and a bus control circuit coupled to the interface means for receiving the first one of the plurality of control signals, a plurality of address values, and a plurality of data values, the bus control circuit providing the plurality of address values and the plurality of data values in the first predetermined format.

Claim 42

A data processor, comprising: a central processing unit for providing a plurality of control signals, a plurality of address values, and a plurality of data values; and a system integration circuit coupled to the data processor for receiving the plurality of control signals, the plurality of address values, and the plurality of data values, the system integration circuit generating a first control signal enabling the data processor to execute a show cycle, the system integration circuit providing the plurality of address values and the plurality of data values in a first predetermined format on a multiplexed bus when the first one of the plurality of control signals indicates the data processor is executing the show cycle, the first predetermined format including a first one of the plurality of data values which is associated with a first address value and is accessed during a first bus cycles, the system integration circuit providing the first one of the plurality of data values to the multiplexed bus during a second cycle in which a second one of the plurality of address values is provided to the multiplexed bus; wherein the system integration circuit comprises: interface means coupled to the central processing unit for receiving the first one of the plurality of control signals, the plurality of address values, and the plurality of data values; and a bus control circuit coupled to the interface means for receiving the first one of the plurality of control signals, a plurality of address values, and a plurality of data values, the bus control circuit providing the plurality of address values and the plurality of data values in the first predetermined format.