Speeding up the response time of the direct multiplex control transfer facility

Claim 1

A microprogrammed data processing system includes a central processing unit (CPU), a main memory for storing a plurality of data bytes in each addressed location, and a plurality of mass storage controllers, all coupled in common to a system bus for transferring a block of data bytes between said main memory and said plurality of mass storage controllers over said system bus during data multiplex control (DMC) cycles, and a read only memory for storing a plurality of microprograms, said system further including apparatus for indicating to said CPU which of said plurality of data bytes in said addressed location in said main memory is to be accessed and whether a memory read or a memory write operation is to be performed, said apparatus comprising: first means for generating a request signal when one of said plurality of mass storage controllers requires a data byte from said main memory or has a data byte to send to said main memory; input/output random access memory (I/O RAM) means for storing input/output instruction information including channel number signals for identifying one of said plurality of mass storage controllers; I/O microprocessor means for generating a plurality of I/O address signals, said I/O RAM means having means responsive to said plurality of I/O address signals for reading out onto said system bus said channel number signals; second means in a mass storage controller coupled to receive said channel number signals on said system bus to generate a read/write signal in a first state indicating a main memory read operation and said read/write signal in a second state indicating a main memory write operation; third means for generating a first signal on alternate DMC cycles indicating one of said plurality of data bytes in an addressed location; fourth means coupled to said first means, said second means and said third means and responsive to said request signal, said read/write signal and said first signal for generating a plurality of data request signals; and fifth means, included in said CPU, and responsive to said plurality of data request signals for generating a plurality of address signals; said read only memory coupled to said fifth means and having means responsive to said plurality of address signals for reading out one of a plurality of microprograms for processing said data cycle byte in accordance with one of said plurality of data request signals.