US6214735B1
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Method for planarizing a semiconductor substrate
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-05-18
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Granted: 2001-04-10
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Expires: 2018-05-18
Abstract
Abstract A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.
Inventors
- 👤 Chang-Gyu Kim
- 👤 Ji-Hyun Choi
- 👤 Seok-ji Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:34
CPC Classifications
H; H10; H10P; H10P50/00; H10P95/00; H10P95/06; H10P95/062; H10P95/064
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
117 words
A method for planarizing a semiconductor substrate, comprising the steps of: preparing a semiconductor substrate having an uneven topography including an elevated region and an adjacent recessed region; sequentially forming first and second insulating layers on the elevated and recessed regions; etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges; forming a third insulating layer on the first and second insulating layers, said second insulating layer having a relatively high etch selectivity relative to the first or third insulating layer; and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed.
Claim 2
Independent Claim
117 words
A method for planarizing a semiconductor substrate, comprising the steps of: preparing a semiconductor substrate having an uneven topography including an elevated region and an adjacent recessed region; sequentially forming first and second insulating layers on the elevated and recessed regions; etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges; forming a third insulating layer on the first and second insulating layers, said second insulating layer having a relatively high etch selectivity relative to the first or third insulating layer; and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed.
Claim 3
Dependent Claim
29 words
The method as defined in claim 1 , wherein said second and first insulating layers at upper edges of the elevated region are sputter etched by Ar sputter etching.
Claim 4
Dependent Claim
28 words
The method as defined in claim 1 , wherein said second insulating layer is made of one selected from a group consisting of SiOF, PSG, BN, and BPSG.
Claim 5
Dependent Claim
30 words
The method as defined in claim 1 , wherein said third insulating layer is made of one selected from a group consisting of HDP CVD oxide and ECR CVD oxide.
Claim 6
Dependent Claim
26 words
The method as defined in claim 1 , wherein said elevated region comprises an intermetal dielectric pattern region and the recessed region comprises the semiconductor substrate.
Claim 7
Dependent Claim
24 words
The method as defined in claim 1 , wherein said elevated region comprises the semiconductor substrate and the recessed region comprises a trench region.
Claim 8
Independent Claim
162 words
A method for planarizing a semiconductor substrate, comprising the steps of: preparing a semiconductor substrate having an uneven topography including an elevated region and a recessed region adjacent to each other; sequentially forming first, second and third insulating layers on the elevated and recessed regions by either HDP CVD process or ECR CVD process, said second insulating layer having a high etch selectivity relative to the first or third insulating layer; and wet-etching the third and second insulating layers until an upper surface of the first insulating layer are exposed to form a planarized semiconductor substrate, wherein the second insulating layer is deposited and at the same time etched during formation thereof to remove upper edges of the elevated region faster than the other portions, thereby exposing portions of the first insulating layer, and the third insulating layer is formed on the second insulating layer and the portions of the first insulating layer exposed at the upper edges of the elevated region.
Claim 9
Independent Claim
162 words
A method for planarizing a semiconductor substrate, comprising the steps of: preparing a semiconductor substrate having an uneven topography including an elevated region and a recessed region adjacent to each other; sequentially forming first, second and third insulating layers on the elevated and recessed regions by either HDP CVD process or ECR CVD process, said second insulating layer having a high etch selectivity relative to the first or third insulating layer; and wet-etching the third and second insulating layers until an upper surface of the first insulating layer are exposed to form a planarized semiconductor substrate, wherein the second insulating layer is deposited and at the same time etched during formation thereof to remove upper edges of the elevated region faster than the other portions, thereby exposing portions of the first insulating layer, and the third insulating layer is formed on the second insulating layer and the portions of the first insulating layer exposed at the upper edges of the elevated region.
Claim 10
Dependent Claim
28 words
The method as defined in claim 7 , wherein said second insulating layer is made of one selected from a group consisting of SiOF, PSG, BN, and BPSG.
Claim 11
Dependent Claim
30 words
The method as defined in claim 7 , wherein said third insulating layer is made of one selected from a group consisting of HDP CVD oxide and ECR CVD oxide.
Claim 12
Dependent Claim
26 words
The method as defined in claim 7 , wherein said elevated region comprises an intermetal dielectric pattern region and the recessed region comprises the semiconductor substrate.
Claim 13
Dependent Claim
24 words
The method as defined in claim 7 , wherein said elevated region comprises the semiconductor substrate and the recessed region comprises a trench region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-04-09 | 2004-10-09 | 2005-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-04-09 | 2008-10-09 | 2009-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-04-09 | 2012-10-09 | 2013-04-10 | $7700.00 | Window Closed / Lapsed |