US5946592A
Expired / Lapsed
US
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Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein
Assignee: Winbond Electronics Corp
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Filing: 1998-03-19
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Granted: 1999-08-31
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Expires: 2018-03-19
Abstract
Abstract A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper. All the three HDP-CVD compositions contain the same etching and silicon-containing deposition components so as to improve the CMP efficiency without incurring substantially increased fabrication cost.
Inventors
- 👤 Chi-Fa Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:58
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
261 words
A wafer planarization process for planarizing a semiconductor wafer surface by combining a high density plasma chemical vapor deposition (HDP-CVD) process with a chemical mechanical polishing (CMP) process, said process comprising the steps of: (a) selecting a general HDP-CVD composition containing a predetermined etching component and a predetermined deposition component, wherein said etching component and said deposition component are selected such that a higher etching/deposition component ratio will generally result in a slower removal rate by a subsequent CMP process of an HDP-CVD layer after said HDP-CVD layer is deposited on a substrate from said deposition component with a co-deposition component, and a low etching/deposition component ratio will generally result in a faster removal rate; (b) forming a first HDP-CVD layer on the substrate via an HDP-CVD process using a first HDP-CVD composition, which contains said etching component and said deposition component having a first etching/depositing component ratio; (c) forming a second HDP-CVD layer on the first HDP-CVD layer using a second HDP-CVD composition, wherein said second HDP-CVD composition contains said etching component and said deposition component at a second etching/depositing component ratio; (d) forming a third HDP-CVD layer on the second HDP-CVD layer using a third HDP-CVD composition, wherein said third HDP-CVD composition contains said etching component and said deposition component at a third etching/depositing component ratio; (e) using a chemical mechanical process to remove at least a part of said third HDP-CVD layer using said second HDP-CVD layer as a stopper; (f) further wherein said second etching/depositing component ratio >said first etching/depositing component ratio >said third etching/depositing component ratio.
Claim 2
Dependent Claim
261 words
A wafer planarization process for planarizing a semiconductor wafer surface by combining a high density plasma chemical vapor deposition (HDP-CVD) process with a chemical mechanical polishing (CMP) process, said process comprising the steps of: (a) selecting a general HDP-CVD composition containing a predetermined etching component and a predetermined deposition component, wherein said etching component and said deposition component are selected such that a higher etching/deposition component ratio will generally result in a slower removal rate by a subsequent CMP process of an HDP-CVD layer after said HDP-CVD layer is deposited on a substrate from said deposition component with a co-deposition component, and a low etching/deposition component ratio will generally result in a faster removal rate; (b) forming a first HDP-CVD layer on the substrate via an HDP-CVD process using a first HDP-CVD composition, which contains said etching component and said deposition component having a first etching/depositing component ratio; (c) forming a second HDP-CVD layer on the first HDP-CVD layer using a second HDP-CVD composition, wherein said second HDP-CVD composition contains said etching component and said deposition component at a second etching/depositing component ratio; (d) forming a third HDP-CVD layer on the second HDP-CVD layer using a third HDP-CVD composition, wherein said third HDP-CVD composition contains said etching component and said deposition component at a third etching/depositing component ratio; (e) using a chemical mechanical process to remove at least a part of said third HDP-CVD layer using said second HDP-CVD layer as a stopper; (f) further wherein said second etching/depositing component ratio >said first etching/depositing component ratio >said third etching/depositing component ratio.
Claim 3
Dependent Claim
22 words
The wafer planarization process according to claim 1 wherein said etching component is Ar as said deposition component is SiH 4 .
Claim 4
Dependent Claim
37 words
The wafer planarization process according to claim 1 wherein said pair of etching/deposition components are selected such that a high etching/deposition component ratio will also result in a more efficient gap filling capability of said HDP-CVD composition.
Claim 5
Dependent Claim
27 words
The wafer planarization process according to claim 1 wherein said co-deposition component is a nitrogen- or oxygen-containing component during the preparation of all said three HDP-CVD layers.
Claim 6
Dependent Claim
41 words
The wafer planarization process according to claim 1 wherein said co-deposition component is an oxygen-containing during the preparation of said first and third HDP-CVD layer, and said co-deposition component is a nitrogen-containing component during the preparation of said second HDP-CVD layer.
Claim 7
Dependent Claim
165 words
A wafer planarization process for planarizing a semiconductor wafer surface comprising the steps of: (a) forming a dielectric layer on the wafer surface via a chemical vapor deposition process; (b) forming a stopper layer on said dielectric layer using the same chemical vapor deposition process; and (c) forming a sacrificial layer on said stopper dielectric layer using the same chemical vapor deposition process; and (d) using a chemical mechanical polishing process to remove at least a part of said sacrificial layer using said stopper layer as a stopper; (e) wherein said dielectric layer, said stop layer, and said sacrificial layer are formed during said chemical vapor deposition process using a deposition composition having the same etching and deposition components but with different etching/deposition component ratios such that said stop layer has a slowest removal rate when subject to said chemical mechanical polishing process relative to said dielectric layer and said sacrificial layer, and said sacrificial layer has a higher removal rate than said dielectric layer.
Claim 8
Dependent Claim
165 words
A wafer planarization process for planarizing a semiconductor wafer surface comprising the steps of: (a) forming a dielectric layer on the wafer surface via a chemical vapor deposition process; (b) forming a stopper layer on said dielectric layer using the same chemical vapor deposition process; and (c) forming a sacrificial layer on said stopper dielectric layer using the same chemical vapor deposition process; and (d) using a chemical mechanical polishing process to remove at least a part of said sacrificial layer using said stopper layer as a stopper; (e) wherein said dielectric layer, said stop layer, and said sacrificial layer are formed during said chemical vapor deposition process using a deposition composition having the same etching and deposition components but with different etching/deposition component ratios such that said stop layer has a slowest removal rate when subject to said chemical mechanical polishing process relative to said dielectric layer and said sacrificial layer, and said sacrificial layer has a higher removal rate than said dielectric layer.
Claim 9
Dependent Claim
38 words
The wafer planarization process according to claim 6 wherein said deposition composition also contains an oxygen-containing or nitrogen-containing co-deposition component to form a silicon oxide layer or a silicon nitride layer, respectively by said chemical vapor deposition process.
Claim 10
Dependent Claim
24 words
The wafer planarization process according to claim 6 wherein said chemical vapor deposition process is a high density plasma enhanced chemical vapor deposition process.
Claim 11
Dependent Claim
22 words
The wafer planarization process according to claim 6 wherein said etching component is argon and said deposition component is SiH 4 .
Claim 12
Dependent Claim
33 words
The wafer planarization process according to claim 6 wherein said etching component and said deposition component are selected such that said dielectric layer has a better gap filling capability than said sacrificial layer.
Claim 13
Dependent Claim
60 words
The wafer planarization process according to claim 6 wherein said etching component and said deposition component are selected such that said dielectric layer is formed during said chemical vapor deposition process using a higher ratio of etching/deposition components than said sacrificial layer, and said stopper layer is formed using an ever higher ratio of etching/deposition components than said dielectric layer.
References Cited (Backward Citations)
US5494854A
Cited
JPH09223737A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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