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US6201423B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device, semiconductor system, and digital delay circuit

Assignee: Socionext Inc
•
Filing: 1999-11-24
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Granted: 2001-03-13
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Expires: 2019-11-24
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Abstract

Abstract Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

Inventors

  • 👤 Masao Taguchi
  • 👤 Yoshihiro Takemae

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 10:29
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G11C7/1006; G11C7/1015; G11C7/1039; G11C7/1066; G11C7/1069; G11C7/1072; G11C7/22; G11C7/222; H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; G11C2207/00; G11C2207/002; G11C2207/10; G11C2207/108; H03K2005/00013; H03K2005/00019; H03K2005/00058

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 81 words
A semiconductor system, having a plurality of semiconductor devices interconnected, for outputting data synchronously with a first external signal and inputting data synchronously with a second external signal, wherein a line over which data items output from said semiconductor devices are transmitted, and a line over which the first external signal is transmitted are arranged in parallel with each other, and the transmission direction of the output data items and the transmission direction of the first external signal are the same.
Claim 2
Dependent Claim 81 words
A semiconductor system, having a plurality of semiconductor devices interconnected, for outputting data synchronously with a first external signal and inputting data synchronously with a second external signal, wherein a line over which data items output from said semiconductor devices are transmitted, and a line over which the first external signal is transmitted are arranged in parallel with each other, and the transmission direction of the output data items and the transmission direction of the first external signal are the same.
Claim 3
Dependent Claim 59 words
A semiconductor system according to claim 1 , wherein a line over which data input to said semiconductor devices is transmitted and a line over which the second external signal is transmitted are arranged in parallel with each other, and the transmission direction of the input data and the transmission direction of the second external signal are the same.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-03-12 2004-09-11 2005-03-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-03-12 2008-09-11 2009-03-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-03-12 2012-09-11 2013-03-13 $7700.00 Window Closed / Lapsed

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