A clock signal supply system

Claim 1

A clock supply system used in a computer system having a plurality of blocks (A, B) which are destinations of a supplied clock signal, comprising: means (113, 114) for generating a plurality of clock signals having phases different from each other; a first signal line (211) for transmitting one of said clock signals from said clock generating means (113, 114) to said blocks (A, B); means (120 a - d, 121 a - d) for adjusting the phase of a received clock signal by passing said received clock signal through a variable delay circuit (120 a - d) and comparing (121 a - d) the output signal of said variable delay circuit (120 a - d) with a reference signal (on line 210) for deriving a control signal (126 a - d) which adjusts the delay time of said variable delay circuit (120 a - d) so that its output signal is in phase with said reference signal; characterized by    means (116) for generating a select signal by which one of said clock signals is designated successively; a second signal line (212) for transmitting said select signal from said select signal generating means (116) to said blocks (A, B); means (115) for generating a reference signal on the basis of said clock signals, said reference signal being a phase reference of the clock signal designated by said select signal; a third signal line (210) for transmitting said reference signal from said reference generating means (115) to said blocks (A, B); and a plurality of variable delay circuits (120 a - d) connected in series and a plurality of comparator circuits (121 a - d), whereby a first one of said series-connected delay circuits (120 a) is connected at its input terminal with said first signal line (211), and whereby for each of said variable delay circuit (120 a - d) a corresponding comparator circuit (121 a - d) is provided, each of said comparator circuits (121 a - d) receiving an output signal from the corresponding variable delay circuit (120 a - d), said reference signal from said third signal line (210) and an output signal of a decoder circuit (118), which is controlled by said select signal generating means (116), for successively designating one of said variable delay circuits (120 a - d) for outputting one of a plurality of clock signals (125 a - d) having a different phase from each other and whereby the phase of this outputted clock signal (125 a - d) coincides with said reference signal on said third signal line (210).