EP0127508A2
Expired / Lapsed
EP
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Full floating point vector processor
Assignee: Analogic Corp
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Filing: 1984-05-02
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Granted: —
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Expires: 2004-05-02
Abstract
Abstract The processor includes a master processing unit(12) having DMA I/O means (48), a wide bandwidth data memory (14), an address generator (28) operative to generate addresses for data loaded in the data memory, a concurrently operating pipeline control sequencer (31) operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit (36) responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator (28), the pipeline control sequencer (31), and the master processing unit (12) are configured in parallel. The address generator (28) includes means operative to provide pipeline input and output data dependent address generation.
Inventors
- 👤 John B. Porter
- 👤 David W. Altmann
- 👤 Bruno A. Mattedi
- 👤 Ralph Jones
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 07:54
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/226; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30036; G06F9/38; G06F9/3877; G06F9/3879; G06F9/3885; G06F9/3887; G06F9/38873; G06F9/3893; G06F9/3895
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
319 words
A full floating point vector processor, comprising : a master processing unit; first means coupled to said master processing unit and having an input and an output bus for providing a plurality of addressable memory locations; second means coupled to said first means and to said master processing unit for loading data to be evaluated in said addressable memory locations; third means coupled to said first means and to said master processing unit and operative concurrently with said master processing unit for providing a plurality of time sequential memory read and write addresses, and for providing a selectively delayed control signal; said first means are operable in response to individual ones of said plurality of time sequential memory read addresses to provide the corresponding data loaded at individual ones of said memory read addresses on said output bus and operable in response to individual ones of data memory write addresses to load the corresponding data on said input bus to said write memory address; fourth means coupled to said first means, to said third means, and to said master processing unit and operative concurrently with both said master processing unit and said third means in response to said delayed control signal for providing a plurality of time sequential microinstructions in time-synchronization with corresponding ones of said plurality of time sequential memory read and write addresses; and fifth means coupled to said first means, to said fourth means and concurrently operative with said master processing unit, said third means, and said fourth means in response to said time sequential data on said output bus and to said synchronously supplied microinstructions for evaluating in accordance with said synchronously applied microinstructions one of a preselected plurality of computationally intensive functions on said data on said output bus and for providing a data value on said input bus representative of said evaluation of said selected one of said plurality of computationally intensive functions.
Claim 2
Dependent Claim
319 words
A full floating point vector processor, comprising : a master processing unit; first means coupled to said master processing unit and having an input and an output bus for providing a plurality of addressable memory locations; second means coupled to said first means and to said master processing unit for loading data to be evaluated in said addressable memory locations; third means coupled to said first means and to said master processing unit and operative concurrently with said master processing unit for providing a plurality of time sequential memory read and write addresses, and for providing a selectively delayed control signal; said first means are operable in response to individual ones of said plurality of time sequential memory read addresses to provide the corresponding data loaded at individual ones of said memory read addresses on said output bus and operable in response to individual ones of data memory write addresses to load the corresponding data on said input bus to said write memory address; fourth means coupled to said first means, to said third means, and to said master processing unit and operative concurrently with both said master processing unit and said third means in response to said delayed control signal for providing a plurality of time sequential microinstructions in time-synchronization with corresponding ones of said plurality of time sequential memory read and write addresses; and fifth means coupled to said first means, to said fourth means and concurrently operative with said master processing unit, said third means, and said fourth means in response to said time sequential data on said output bus and to said synchronously supplied microinstructions for evaluating in accordance with said synchronously applied microinstructions one of a preselected plurality of computationally intensive functions on said data on said output bus and for providing a data value on said input bus representative of said evaluation of said selected one of said plurality of computationally intensive functions.
Claim 3
Dependent Claim
19 words
The full floating point vector processor of claim 1, wherein said master processing unit is a 68000 supermicroprocessor chip.
Claim 4
Dependent Claim
16 words
The full floating point vector processor of claim 1, wherein said first means includes static RAM.
Claim 5
Dependent Claim
16 words
The full floating point vector processor of claim 1, wherein first means include interleaved dynamic RAM.
Claim 6
Dependent Claim
52 words
The full floating point vector processor of claim 4, wherein said interleaved dynamic RAM is arranged into even and odd bank pairs operative to provide two words in response to each said time sequential memory read addresses and to accept two values in response to each said time sequential memory write addresses.
Claim 7
Dependent Claim
23 words
The full floating vector processor of claim 1, wherein said second means includes a direct memory acess controller connected to a host interface.
Claim 8
Dependent Claim
24 words
The full floating point vector processor of claim 1, wherein said second means includes a RS-232 interface operatively connected to said master processing unit.
Claim 9
Dependent Claim
24 words
The full floating point vector processor of claim 1, wherein said second means includes a UNIBUS interface operatively connected to said master processing unit.
Claim 10
Dependent Claim
24 words
The full floating point vector processor of claim 1, wherein said second means include a MULTIBUS interface operatively connected to said master processing unit.
Claim 11
Dependent Claim
22 words
The full floating point vector processor of claim 1, further including at least two I/O ports operatively connected to said first means.
Claim 12
Dependent Claim
97 words
The full floating point vector processor of claim 1, wherein said third means includes an address generator having a control store RAM loadable by said master processing unit with address generation control loops, a start register loadable by said master processing unit with a start address corresponding to a selected one of said address genration control loops, and an address generator arithmetic and logical unit connected to said address generator control store RAM and operative in response to said selected address generator control loop for providing said plurality of time sequential data memory read and write addresses.
Claim 13
Dependent Claim
28 words
The full floating point vector processor of claim 11, further including a write address FIFO connected between said address generator arithmetic and logical unit and said first means.
Claim 14
Dependent Claim
24 words
The full floating point vector processor of claim 11, further including a write data FIFO connected between said input bus and said fifth means.
Claim 15
Dependent Claim
82 words
The full_floating point vector processor of claim 11, wherein said fourth means includes a pipeline control sequencer having a pipeline control sequencer control store RAM loadable by said master processing unit with pipeline control sequencer microinstruction loops each corresponding to one of said plurality of computationally intensive functions to be evaluated, and wherein said pipeline control sequencer includes a start address register loadable by said address generator with the start address of a selected one of said plurality of computationally intensive functions.
Claim 16
Dependent Claim
93 words
The full floating point vector processor of claim 1, wherein said fifth means includes a dynamically configurable multifunction pipelined arithmetic and logical unit having an M register file and a Z register file selectively interconnectable under microinstruction control by way of both a feedforward and a feedback path; and wherein each of said M and said Z register files are 4 port devices having two input ports and two output ports and are operative in response to individual ones of said plurality of microinstructions to provide two writes thereinto and two reads therefrom.
Claim 17
Dependent Claim
66 words
The full floating point vector processor of claim 15, wherein said dynamically configurable multifunction pipelined arithmetic and logical unit includes an arithmetic and logical unit and a sign bit latch, said sign bit latch connected between said Z file and said arithmetic and logical unit and operative in response to said microinstructions to provide said arithmetic and logical unit with a data dependent decision making capability.
Claim 18
Dependent Claim
236 words
A vector processor, comprising : a clock for providing a sequence of discret clocking signals; a data memory for storing data vectors to be evaluated and for storing data values after evaluation; a master processing unit coupled to said data memory and to said clock; an interface connected to said master processing unit and coupled to said data memory for loading said data memory with said data vectors to be evaluated and for offloading said data values after evaluation; an address generator, coupled to said data memory and to said master processing unit, operative in response to said clock for controllably providing a data memory read address upon the occurrence of each clocking signal; a pipeline control sequencer, connected to said master processing unit and coupled to said address generator and concurrently operative therewith, operative in response to said clock and to said address generator for providing a microinstruction upon the occurrence of every clocking signal having a fully programmable horizontal format bit field concurrently with corresponding ones of said plurality of data memory write addresses and in time synchronization therewith; and a pipelined arithmetic and logical unit coupled to said pipeline control sequencer and to said data memory and operative in response to individual ones of said microinstructions and said clocking signal for evaluating selected ones of a plurality of computationally intensive functions on the data specified by said plurality of data memory read addresses.
Claim 19
Dependent Claim
236 words
A vector processor, comprising : a clock for providing a sequence of discret clocking signals; a data memory for storing data vectors to be evaluated and for storing data values after evaluation; a master processing unit coupled to said data memory and to said clock; an interface connected to said master processing unit and coupled to said data memory for loading said data memory with said data vectors to be evaluated and for offloading said data values after evaluation; an address generator, coupled to said data memory and to said master processing unit, operative in response to said clock for controllably providing a data memory read address upon the occurrence of each clocking signal; a pipeline control sequencer, connected to said master processing unit and coupled to said address generator and concurrently operative therewith, operative in response to said clock and to said address generator for providing a microinstruction upon the occurrence of every clocking signal having a fully programmable horizontal format bit field concurrently with corresponding ones of said plurality of data memory write addresses and in time synchronization therewith; and a pipelined arithmetic and logical unit coupled to said pipeline control sequencer and to said data memory and operative in response to individual ones of said microinstructions and said clocking signal for evaluating selected ones of a plurality of computationally intensive functions on the data specified by said plurality of data memory read addresses.
Claim 20
Dependent Claim
27 words
The vector processor of claim 17, further including a write address FIFO connected between said address generator and the input of the pipelined arithmetic and logical unit.
Claim 21
Dependent Claim
39 words
The vector processor of claim 17, wherein said address generator is operative to generate write data addresses, and further including a write data FIFO connected between the output of said pipelined arithmetic and logical unit and said data memory.
Claim 22
Dependent Claim
33 words
The vector processor of claim 18, wherein said write adress FIFO is coupled to said pipeline control sequencer and is controleld by a preselected bit field of said fully programmable horizontal format microinstructions.
Claim 23
Dependent Claim
34 words
The vector processor of claim 19, wherein said write data FIFO is coupled to said pipeline control sequencer and is controlled by a preselected bit field of said fully programmable horizontal format micro- instructions.
Claim 24
Dependent Claim
67 words
22 . The vector processor of claim 17, wherein said pipelined arithmetic and logical unit includes a M file register and a Z file register coupled to said pipeline control sequencer, each having two inputs and two outputs, and operative in response to preselected bit fields of said horizontal format fully programmable microinstructions for performing two reads and two writes upon the occurence of each clock pulse.
Claim 25
Dependent Claim
58 words
The vector processor of claim 22, wherein said pipelined arithmetic and logical unit includes an arithmetic and logical unit connected to said Z file via a sign latch operative under a preselected bit field of said fully programmable horizontal format . microinstructions to provide said arithmetic and logical unit with sign information to controllably provide data-dependent decision making.
Claim 26
Dependent Claim
57 words
The vector processor of claim 17, wherein said address generator includes an arithmetic and logical unit, and further includes at least one latch, enabled by a preselected bit field of said fully programmable horizontal format microinstructions, connected between said data memory and said address generator arithmetic and logical unit, for providing data memory output dependent address generation.
Claim 27
Dependent Claim
61 words
The vector processor of claim 17, wherein said address generator includes an address generator arithmetic and logical unit, and further includes at least one latch, enabled by a preselected bit field of said fully programmable horizontal format microinstructions connected between said pipelined arithmetic and logical unit and said address generator arithmetic and logical unit, for providing pipeline output dependent address generation.
Claim 28
Dependent Claim
64 words
The vector processor of claim 17, further including a write address FIFO connected between said pipelined arithmetic and logical unit and said data memory, and a counter connected between said address generator and said write address FIFO, said write address FIFO enabled by a preselected bit field of said fully programmable horizontal format microinstruction and said counter having counted down to a predetermined value.
Claim 29
Dependent Claim
13 words
The vector processor of claim 17, wherein said interface is a UNIBUS interface.
Claim 30
Dependent Claim
13 words
The vector processor of claim 17, wherein said interface is a MULTIBUS interface.
Claim 31
Dependent Claim
16 words
29 . The vector processor of claim 17, wherein said interface is a RS-232 serial line.
Claim 32
Dependent Claim
19 words
The vector processor of claim 17, further including at least two auxiliary I/O ports connected to said data memory.
Claim 33
Dependent Claim
39 words
The vector processor of claim 17, wherein said data memory includes-dynamic RA M connected in parallel even and odd bank pairs and operative in response to each address specified by said address generator to serially provide two data words.
Claim 34
Dependent Claim
217 words
A vector processor operative in one of a fixed or a floating point format and in one of a tightly coupled, loosely coupled, and an uncoupled mode; comprising : a clock for provididing clock pulses; a master processing unit coupled to said clock; a data memory coupled to said clock and to said processing unit; means connected to said clock and to said master processing unit for providing direct memory access for loading data into and out of said data memory; a first processor connected in parallel with said master processing unit and coupled to said clock and said data memory for providing data memory write and read addresses upon each clock pulse occurrence a second processor connected in parallel with sa=d master processing unit and said first processor coupled to said clock and operative in response to said first processor for providing a horizontal format microinstruction upon each clock pulse occurence in time synchronization with individual ones of said data memory write addresses; and a controllably configurable pipelined arithmetic and logical unit connected to said data memory and said second processor and coupled to said clock and responsive to the data values specified by said data memory write addresses and said micro- instructions upon every clock pulse for evaluating a computationally intensive function of said data.
Claim 35
Dependent Claim
217 words
A vector processor operative in one of a fixed or a floating point format and in one of a tightly coupled, loosely coupled, and an uncoupled mode; comprising : a clock for provididing clock pulses; a master processing unit coupled to said clock; a data memory coupled to said clock and to said processing unit; means connected to said clock and to said master processing unit for providing direct memory access for loading data into and out of said data memory; a first processor connected in parallel with said master processing unit and coupled to said clock and said data memory for providing data memory write and read addresses upon each clock pulse occurrence a second processor connected in parallel with sa=d master processing unit and said first processor coupled to said clock and operative in response to said first processor for providing a horizontal format microinstruction upon each clock pulse occurence in time synchronization with individual ones of said data memory write addresses; and a controllably configurable pipelined arithmetic and logical unit connected to said data memory and said second processor and coupled to said clock and responsive to the data values specified by said data memory write addresses and said micro- instructions upon every clock pulse for evaluating a computationally intensive function of said data.
Claim 36
Dependent Claim
57 words
The vector processor of claim 32, wherein said pipelined arithmetic and logical unit includes a first register file and a second register file selectively interconnectable by a feedforward and a feedback path under microinstruction control and operative upon each clock pulse to perform two writes into the register files and two reads out of the register files.
Claim 37
Dependent Claim
33 words
The vector processor of claim 33, wherein each of said register files has two input and two output ports, and wherein one of said writes is to an address specified for a read.
Claim 38
Dependent Claim
45 words
The vector processor of claims 34, wherein said output ports of said first register file are connected to the input ports of a two input port multiplier having two output ports that are connected to one of the input ports of the second register file.
Claim 39
Dependent Claim
50 words
The vector processor of claim 35, wherein the output ports of the second register file are connected to the two input ports of a two input port arithmetic and logical unit having one output port that is connected back to one of the input ports of the second register file.
Claim 40
Dependent Claim
47 words
The vector processor of claim 36, further including a sign latch connected between one of the output ports of said register file and said arithmetic and logical unit and operative under microinstruction and operative to provide data dependent decision making capability for said arithmetic and logical unit.
Claim 41
Dependent Claim
38 words
The vector processor of claim 37, wherein said pipelined arithmetic and logical unit includes means connected between said data memory and said first register file under microinstruction control for pivoting one of on-the-fly fixed and floating format conversion.
References Cited (Backward Citations)
No citation records indexed.
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