High speed manchester encoder

Claim 2

A high speed manchester encode comprising: (a) input means for receiving serial data, (b) synchronizing means coupled to said input means for providing a first data stream and a second delayed and inverted data stream, (c) a multiplexer coupled to said synchronizing means for selecting either of said data streams to provide a manchester encoded data stream output.

Claim 3

The encoder of claim 1 wherein said synchronizing means includes a first latch circuit coupled to said input means and being latched by a first clock source and a second latch circuit coupled to said first latch circuit and being latched by a second clock source 180° out of phase with the first clock source.

Claim 4

The encoder of claim 2 wherein said first and second clock sources are generated from a master clock source.

Claim 5

The encoder of claim 3 wherein said multiplexer is of the time dimension type and responds to a logic zero to select said first data stream and responds to a logic one to select said second data stream.

Claim 6

A high speed manchester encoder comprising: (a) a source of serial data, (b) latch circuit means for converting said serial data to a first data stream synchronized with a first clock source and a second data stream that is inverted and synchronized with a second inverted clock source, (c) a multiplexer coupled to said latch circuit means for selecting either of said data streams determined by the state of the clock source applied to the select input.

Claim 7

A high speed manchester encoder comprising: (a) a source of serial data, (b) latch circuit means for converting said serial data to a first data stream synchronized with a first clock source and a second data stream that is inverted and synchronized with a second inverted clock source, (c) a multiplexer coupled to said latch circuit means for selecting either of said data streams determined by the state of the clock source applied to the select input.

Claim 8

The encoder of claim 5 wherein said latch circuit means includes: (a) a first D latch circuit having a first input coupled to said data source, a second input coupled to the first clock source and having an output, (b) a second D latch circuit having a first input coupled to the output of said first D latch circuit, a second input coupled to the inverted clock source and having an output.

Claim 9

The encoder of claim 6 wherein the select clock source of said multiplexer is of the same frequency as said first and second clock sources.

Claim 10

A high speed manchester encoder comprising: (a) a source of input serial data, (b) a master clock source, (c) a clock pulse generator coupled to said master clock source for generating two clocks 180° out of phase with each other, (d) a first D latch circuit having a first input coupled to said data source, a second input coupled to one of said clocks and having an output, (e) a second D latch circuit having a first input coupled to the output of said first D latch circuit, a second input coupled to the other of said clocks and having an inverted output, (f) a multiplexer having a first input coupled to the output of said first D circuit, a second input coupled to the inverted output of said second D latch circuit, a select input coupled to said master clock source and having an output.

Claim 11

A high speed manchester encoder comprising: (a) a source of input serial data, (b) a master clock source, (c) a clock pulse generator coupled to said master clock source for generating two clocks 180° out of phase with each other, (d) a first D latch circuit having a first input coupled to said data source, a second input coupled to one of said clocks and having an output, (e) a second D latch circuit having a first input coupled to the output of said first D latch circuit, a second input coupled to the other of said clocks and having an inverted output, (f) a multiplexer having a first input coupled to the output of said first D circuit, a second input coupled to the inverted output of said second D latch circuit, a select input coupled to said master clock source and having an output.