US6198784B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods of synchronizing a personal handy-phone system station and phase lock loops
Assignee: NXP BV
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Filing: 1999-10-20
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Granted: 2001-03-06
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Expires: 2019-10-20
Abstract
Abstract The present invention provides methods of synchronization, personal handy-phone system stations, and phase lock loops. Synchronization of a personal handy-phone system station with a telecommunication network, and another communication station are provided. One method of synchronization comprises: providing a counter configured to generate a plurality of counter values; storing a first counter value; detecting a reference event; latching a second counter value responsive to the detecting of the reference event; comparing the first counter value and the second counter value to detect phase drift; and compensating for phase drift responsive to the comparing.
Inventors
- 👤 Denis Archambaud
- 👤 Patrick Feyfant
- 👤 Philippe Gaglione
- 👤 Varenka Martin
- 👤 Oliver Weigelt
- 👤 Laurent Winckel
- 👤 Satoshi Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:17
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/08
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
88 words
A synchronization method comprising: receiving a reference signal having a plurality of reference events; generating a timing signal independent of the reference signal; generating a bit rate signal responsive to the timing signal, the generating comprising: utilizing a counter, generating a plurality of counter values responsive to the timing signal; and decoding the counter values to establish the bit rate signal; detecting the plurality of reference events within the reference signal after the receiving; and adjusting the bit rate signal responsive to the detecting of the reference events.
Claim 2
Dependent Claim
88 words
A synchronization method comprising: receiving a reference signal having a plurality of reference events; generating a timing signal independent of the reference signal; generating a bit rate signal responsive to the timing signal, the generating comprising: utilizing a counter, generating a plurality of counter values responsive to the timing signal; and decoding the counter values to establish the bit rate signal; detecting the plurality of reference events within the reference signal after the receiving; and adjusting the bit rate signal responsive to the detecting of the reference events.
Claim 3
Dependent Claim
21 words
The method according to claim 1 wherein the reference events individually comprise a unique word of a personal handy-phone system slot.
Claim 4
Dependent Claim
22 words
The method according to claim 1 further comprising utilizing the timing signal as a timing reference within a personal handy-phone system station.
Claim 5
Dependent Claim
36 words
The method according to claim 1 wherein the generating of the bit rate signal comprises: decoding the counter values to establish the bit rate signal having a frequency different than a frequency of the timing signal.
Claim 6
Dependent Claim
18 words
The method according to claim 1 wherein the adjusting comprises resetting a current counter value of the counter.
Claim 7
Dependent Claim
19 words
The method according to claim 1 wherein the generating of the timing signal comprises using a voltage controlled oscillator.
Claim 8
Dependent Claim
23 words
The method according to claim 6 wherein the adjusting comprises controlling a voltage of a control signal applied to the voltage controlled oscillator.
Claim 9
Dependent Claim
19 words
The method according to claim 1 further comprising detecting phase drift responsive to the detecting of the reference events.
Claim 10
Dependent Claim
17 words
The method according to claim 8 wherein the adjusting is responsive to the detecting of phase drift.
Claim 11
Dependent Claim
47 words
The method according to claim 8 wherein the detecting phase drift comprises: storing a first counter value responsive to detecting an initial reference event; latching a second counter value responsive to detecting a subsequent reference event; and comparing the first counter value and the second counter value.
Claim 12
Dependent Claim
25 words
The method according to claim 10 wherein the comparing of the counter values and the adjusting of the bit rate signal comprise using a processor.
Claim 13
Dependent Claim
125 words
A phase lock loop comprising: an input operable to receive a reference signal having a plurality of reference events; a clock generator configured to generate a timing signal independent of the reference signal and to generate a bit rate signal responsive to the timing signal, the clock generator comprising: a counter configured to count a plurality of counter values; and an output decoder operable to generate the bit rate signal responsive to the counter values; and a processor coupled with the input and the clock generator, the processor being configured to detect the reference events, and to detect phase drift within the reference signal responsive to the detection of the reference events and to adjust the bit rate signal to compensate for the phase drift.
Claim 14
Dependent Claim
125 words
A phase lock loop comprising: an input operable to receive a reference signal having a plurality of reference events; a clock generator configured to generate a timing signal independent of the reference signal and to generate a bit rate signal responsive to the timing signal, the clock generator comprising: a counter configured to count a plurality of counter values; and an output decoder operable to generate the bit rate signal responsive to the counter values; and a processor coupled with the input and the clock generator, the processor being configured to detect the reference events, and to detect phase drift within the reference signal responsive to the detection of the reference events and to adjust the bit rate signal to compensate for the phase drift.
Claim 15
Dependent Claim
31 words
The phase lock loop according to claim 12 wherein the output decoder is operable to generate the bit rate signal having a frequency different than a counting frequency of the counter.
Claim 16
Dependent Claim
27 words
The phase lock loop according to claim 12 wherein the processor is configured to apply a reference counter value to the counter to compensate for phase drift.
Claim 17
Dependent Claim
24 words
The phase lock loop according to claim 12 wherein the clock generator further comprises a voltage control oscillator configured to generate the timing signal.
Claim 18
Dependent Claim
27 words
The phase lock loop according to claim 15 wherein the processor is configured to adjust a voltage of a control signal applied to the voltage controlled oscillator.
Claim 19
Dependent Claim
24 words
The phase lock loop according to claim 15 wherein the processor is configured to compare the plurality of counter values to detect phase drift.
Claim 20
Dependent Claim
23 words
The phase lock loop according to claim 12 wherein the reference events individually comprise a unique word of a personal handy-phone system slot.
Claim 21
Dependent Claim
18 words
The phase lock loop according to claim 12 wherein the reference signal is generated by a telecommunication network.
Claim 22
Dependent Claim
111 words
A synchronization method comprising: receiving a reference signal having a plurality of reference events; generating a timing signal independent of the reference signal; generating a bit rate signal responsive to the timing signal; detecting the plurality of reference events within the reference signal after the receiving; detecting phase drift responsive to the detecting of the reference events, the detecting phase drift comprising: storing a first counter value responsive to detecting an initial reference event; latching a second counter value responsive to detecting a subsequent reference event; and comparing the first counter value and the second counter value; and adjusting the bit rate signal responsive to the detecting of the reference events.
Claim 23
Dependent Claim
111 words
A synchronization method comprising: receiving a reference signal having a plurality of reference events; generating a timing signal independent of the reference signal; generating a bit rate signal responsive to the timing signal; detecting the plurality of reference events within the reference signal after the receiving; detecting phase drift responsive to the detecting of the reference events, the detecting phase drift comprising: storing a first counter value responsive to detecting an initial reference event; latching a second counter value responsive to detecting a subsequent reference event; and comparing the first counter value and the second counter value; and adjusting the bit rate signal responsive to the detecting of the reference events.
Claim 24
Dependent Claim
26 words
The synchronization method according to claim 20 wherein the comparing of the counter values and the adjusting of the bit rate signal comprise using a processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-05 | 2004-09-04 | 2005-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-05 | 2008-09-04 | 2009-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-05 | 2012-09-04 | 2013-03-06 | $7700.00 | Window Closed / Lapsed |