Digital phase alignment and integrated multichannel transceiver employing same

Claim 2

A synchronizer for phase aligning an input signal, having a data transition, with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal, said phase of the sampling clock signal being offset from the reference clock signal when the reference clock signal is in phase with the input signal; selection means for detecting a phase relationship between said sampling clock signal and at least some of said input replicas, and for identifying based thereon one of said input replicas as synchronized with said sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and output means for retiming and for outputting the synchronous replica as a data output signal phase aligned with the reference clock signal, said output means for retiming the synchronous replica including means for compensating for said clock adjustment means' sampling clock signal phase offset relative to the reference clock signal when the reference clock signal is in phase with the input signal.

Claim 3

The synchronizer of claim 1, wherein said clock adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal.

Claim 4

The synchronizer of claim 1, wherein said delay circuit, said clock adjustment means, said selection means and said output means are each digitally implemented.

Claim 5

The synchronizer of claim 1, wherein the synchronous replica comprises an input replica of said input replicas that is most synchronized with the sampling clock signal.

Claim 6

The synchronizer of claim 1, wherein the synchronous replica comprises a one of said input replicas having a phase which leads the sampling clock signal.

Claim 7

The synchronizer of claim 1, wherein said output means further includes compensation means for evaluating the synchronous replica for cycle slip, and wherein when found, the data output signal comprises a cycle-slip compensated data output signal, said cycle-slip compensated data output signal being synchronized with the reference clock signal.

Claim 8

The synchronizer of claim 6, wherein said selection means includes means for storing a previous synchronous replica, and wherein said compensation means includes means for comparing the phase of the synchronous replica with a phase of the previous synchronous replica and wherein said cycle slip evaluation includes means for examining the synchronous replica and the previous synchronous replica for a predefined phase difference.

Claim 9

The synchronizer of claim 7, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before outputting of the synchronous replica as the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.

Claim 10

The synchronizer of claim 1, further comprising an elastic buffer and byte synchronizer, coupled in series to the output means, for receiving the data output signal, buffering said data output signal and then for byte synchronizing a resultant buffered data output signal.

Claim 11

The synchronizer of claim 1, wherein said selection means includes a multiplexer circuit for selection of the synchronous replica from the input replicas output by the delay circuit.

Claim 12

A synchronizer for phase aligning an input signal with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; means for acquiring phase states for each input replica relative to the reference clock signal, including means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state; selection means, coupled to said means for acquiring phase states, for identifying based on phase states one of the input replicas as synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and means for outputting the synchronous replica as a data output signal phase aligned with the reference clock signal.

Claim 13

A synchronizer for phase aligning an input signal with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; means for acquiring phase states for each input replica relative to the reference clock signal, including means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state; selection means, coupled to said means for acquiring phase states, for identifying based on phase states one of the input replicas as synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and means for outputting the synchronous replica as a data output signal phase aligned with the reference clock signal.

Claim 14

The synchronizer of claim 11, wherein said delay circuit, said phase state acquiring means, said selection means and said outputting means are each digitally implemented.

Claim 15

The synchronizer of claim 11, wherein the synchronous replica identified by said selection means comprises an input replica most closely synchronized with the reference clock signal.

Claim 16

The synchronizer of claim 11, wherein the synchronous replica identified by said selection means comprises a one of said input replicas having a phase which leads the reference clock signal.

Claim 17

The synchronizer of claim 11, wherein said means for outputting includes compensation means for evaluating the synchronous replica for cycle slip, and when identified, for outputting the data output signal as a cycle-slip compensated data output signal synchronized with the reference clock signal.

Claim 18

The synchronizer of claim 15, wherein said selection means includes means for saving a previous synchronous replica, and said compensation means includes means for comparing the phase of the synchronous replica with a phase of the previous synchronous replica, said means for evaluating cycle slip including means for identifying a phase difference between the phase of the synchronous replica and the phase of the previous synchronous replica.

Claim 19

The synchronizer of claim 16, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more that 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.

Claim 20

The synchronizer of claim 17, wherein said selection means includes means for determining a phase change direction between the synchronous replica and the previous synchronous replica and for providing based thereon a corresponding lead/lag signal to said outputting means.

Claim 21

The synchronizer of claim 11, further comprising clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal, the phase of the sampling clock signal being offset from the reference clock signal when the reference clock signal is in phase with the input signal; and wherein: said selection means includes means for detecting a phase relationship between the sampling clock signal and at least some of the input replicas, and for identifying based thereon one of said input replicas is synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and said means for outputting includes means for retiming the synchronous replica by compensating for said clock adjustment means' sampling clock signal phase offset relative to the reference clock signal when the reference clock signal is substantially in phase with the input signal.

Claim 22

The synchronizer of claim 19, wherein said clock adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal.

Claim 23

A synchronizer for phase aligning an input signal with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; selection means, coupled to the delay circuit, for identifying one of said input replicas as synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and compensation means for evaluating the synchronous replica for cycle slip, and for outputting based thereon, a cycle-slip compensated data output signal whenever a cycle slip is determined, said cycle-slip compensated data output signal being synchronized with the reference clock signal.

Claim 24

A synchronizer for phase aligning an input signal with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; selection means, coupled to the delay circuit, for identifying one of said input replicas as synchronized with the reference clock signal, said identified one of the input replicas comprising a synchronous replica; and compensation means for evaluating the synchronous replica for cycle slip, and for outputting based thereon, a cycle-slip compensated data output signal whenever a cycle slip is determined, said cycle-slip compensated data output signal being synchronized with the reference clock signal.

Claim 25

The synchronizer of claim 21, wherein said delay circuit, said selection means and said compensation means is each digitally implemented.

Claim 26

The synchronizer of claim 21, wherein said synchronous replica comprises a one of said input replicas most closely synchronized with the reference clock signal.

Claim 27

The synchronizer of claim 21, wherein said synchronous replica comprises a one of said input replicas having a phase which leads the reference clock signal.

Claim 28

The synchronizer of claim 21, wherein said selection means includes means for saving a previous synchronous replica, and said compensation means includes means for comparing the phase of the synchronous replica with a phase of the previous synchronous replica, said compensation means' cycle slip evaluating being based on a phase difference between the phase of the synchronous replica and the phase of the previous synchronous replica.

Claim 29

The synchronizer of claim 25, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.

Claim 30

The synchronizer of claim 26, wherein said selection means further comprises means for determining phase change direction between the synchronous replica and the previous synchronous replica, and for outputting based thereon a corresponding lead/lag signal to said compensating means for use in said cycle slip evaluation.

Claim 31

The synchronizer of claim 21, further comprising output means for outputting the synchronous replica as the data output signal synchronized with the reference clock signal when no cycle slip is determined by said compensation means.

Claim 32

A synchronizer for phase aligning an input signal, having a data transition, with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal; means for acquiring phase states for the input replicas relative to the sampling clock signal, said means for acquiring phase states including means for filtering incorrect phase states; selection means, coupled to said means for acquiring phase states, for identifying based on acquired phase states one of the input replicas as synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and retiming and cycle-slip compensation means for outputting a cycle-slip compensated data output signal closely synchronized with the reference clock signal, said retiming means including means for adjusting the phase of the synchronous replica when the sampling clock signal is phase offset from the reference clock signal, said phase compensating of the synchronous replica being equal to the phase offset of the sampling clock signal relative to the reference clock signal.

Claim 33

A synchronizer for phase aligning an input signal, having a data transition, with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal; means for acquiring phase states for the input replicas relative to the sampling clock signal, said means for acquiring phase states including means for filtering incorrect phase states; selection means, coupled to said means for acquiring phase states, for identifying based on acquired phase states one of the input replicas as synchronized with the sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and retiming and cycle-slip compensation means for outputting a cycle-slip compensated data output signal closely synchronized with the reference clock signal, said retiming means including means for adjusting the phase of the synchronous replica when the sampling clock signal is phase offset from the reference clock signal, said phase compensating of the synchronous replica being equal to the phase offset of the sampling clock signal relative to the reference clock signal.

Claim 34

The synchronizer of claim 29, wherein said delay circuit, said clock adjustment means, said means for acquiring phase states, said selection means, and said retiming and cycle slip compensation means is each digitally implemented.

Claim 35

The synchronizer of claim 29, wherein said clock adjustment means includes means for providing the sampling clock signal synchronous with the reference clock signal when the reference clock signal is phase offset from the input signal.

Claim 36

The synchronizer of claim 31, wherein said adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal.

Claim 37

The synchronizer of claim 29, wherein the synchronous replica comprises an input replica most synchronized with the sampling clock signal.

Claim 38

The synchronizer of claim 29, wherein the synchronous replica comprises a one of said input replicas having a phase which leads the sampling clock signal.

Claim 39

The synchronizer of claim 29, wherein said selection means includes means for storing a previous synchronous replica, and wherein said compensation means includes means for comparing the phase of the synchronous replica with the phase of the previous synchronous replica and wherein said cycle slip evaluation includes means for examining the synchronous replica and the previous synchronous replica for a predefined phase difference.

Claim 40

The synchronizer of claim 35, wherein said compensation means includes means for deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and wherein said compensation means includes means for adding an output data bit before outputting of the synchronous replica as the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.

Claim 41

The synchronizer of claim 36, wherein said selection means includes means for determining a phase change direction between the synchronous replica and the previous replica and for providing to said retiming and cycle slip compensation means a corresponding lead/lag signal.

Claim 42

The synchronizer of claim 29, wherein said means for acquiring phase states includes means for evaluating the acquired phase states, beginning with a phase state corresponding with a least delayed input replica, for detecting a first phase state transition and when detected, for setting each acquired phase state subsequent thereto to a predefined, set phase state.

Claim 45

The method of claim 39, wherein said acquiring step (c) includes evaluating each acquired phase state, beginning with a phase state corresponding with a least delayed input replica, and detecting a first phase state transition and when detected, setting each acquired phase state subsequent thereto to a predefined, set phase state.

Claim 46

The method of claim 39, wherein said selecting step (e) includes selecting an input replica most closely synchronized with the reference clock signal.

Claim 47

The method of claim 39, wherein said selecting step (e) includes selecting a one of said input replicas having a phase which leads the reference clock signal.

Claim 48

The method of claim 39, further comprising the step of saving a previous synchronous replica and wherein said cycle-slip evaluating includes identifying a phase offset between the synchronous replica and the previous synchronous replica.

Claim 49

The method of claim 43, further comprising the step of deleting the data output signal when the phase of the synchronous replica lags by more than 360° the phase of the previous synchronous replica, and adding an output data bit before the data output signal when the phase of the synchronous replica leads the phase of the previous synchronous replica by more than 360°.