Digital bit rate converter

Claim 1

In a digital data transmission system having a transmitter and a receiver, apparatus at said transmitter for increasing the bit rate f 1 of a digital data signal and forming a composite line signal of bit rate f 2 having a predetermined framing pattern, said apparatus comprising: means for providing a first clock signal of bit rate f 1 ; timing means responsive to said first clock signal, said timing means providing a second clock signal of bit rate f 2 wherein, f 2 is related to f 1 such that f 1 /(f.sub. 2 - f 1 ) is a rational, fixed number, said timing means comprising: a phase-locked loop having a phase comparator, a low pass filter, a digital voltage-controlled oscillator, and a feedback circuit of said phase-locked loop further comprising: means for sequentially counting predetermined numbers of bits from said oscillator and generating a third binary clock signal having a bit rate of (f 2 - f 1 ) and a pulse width of 1/f 2 ; and logic means interrupting said second binary clock signal in response to said third binary clock signal; means for upconverting said digital data signal to an upconverted bit stream comprised of nonredundant sampled data bits of said f 2 bit rate, and having periodic signal gaps which have a duration of 1/f 2 and which occur at a rate of f 2 - f 1 , said upconverter comprising: means responsive to said first and second clock signals for generating a fourth binary clock signal f 1 ' having an average bit rate f 1 and associated periodic gaps therein of duration 1/f 2 occurring at an average rate of (f 2 - f 1 ) with an average bit rate between said gaps of f 2 ; and means sampling digital data signal in response to said fourth clock signal; means for generating stuffed bits, said bits including framing bits having a predetermined pulse sequence; and means for interleaving said upconverted bit stream with said stuffed bits forming said composite line signal.