US5777499A
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US
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Digital frequency control circuit phase control circuit and PLL circuit
Assignee: Socionext Inc
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Filing: 1996-04-10
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Granted: 1998-07-07
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Expires: 2016-04-10
Abstract
Abstract An oscillating circuit 30 outputs a signal .o slashed. o whose pulse cycle T is a linear function T=kS+m of a control input value S. A frequency control circuit 10, every time a counter 11 counts a number Nr of pulses of a reference signal .o slashed. r , calculates S=No-m/k, where No is a count of .o slashed. o counted by the counter 12, makes a judgement on convergence of .o slashed. o based upon the difference between input and output values of a register 14, makes the register 14 hold S, updates Nr=S+m/k and clears the counter 12 to 0. A digital phase control circuit 20 judges a advance/delay of the phase of .o slashed. o relative to .o slashed. r with a phase comparator circuit 21, decrements/increments a count with a counter circuit 22 every time a judgement on the advance/delay of the phase is made and when the result of the judgement on the advance/delay of the phase is reversed from the previous result of that, changes the count to a value that is half the number of times that the same judgement was made successively before the reversal.
Inventors
- 👤 Toru Takaishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:13
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/113; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03L7/085
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
129 words
A digital frequency control circuit for controlling in such a way that a frequency of an output signal of an oscillating circuit approaches a frequency of a reference signal, a pulse cycle T of said output signal being approximately a linear function of a control input value S, namely T=kS+m, comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said output signal as a feedback signal; a register holding said control input value S; and a calculation and control circuit, when said first counter have counted a number Nr of pulses, calculating S=No-m/k, where No being a count of said second counter, making said register hold S, equalizing said number Nr for a next value to No and initializing the count No.
Claim 2
Dependent Claim
129 words
A digital frequency control circuit for controlling in such a way that a frequency of an output signal of an oscillating circuit approaches a frequency of a reference signal, a pulse cycle T of said output signal being approximately a linear function of a control input value S, namely T=kS+m, comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said output signal as a feedback signal; a register holding said control input value S; and a calculation and control circuit, when said first counter have counted a number Nr of pulses, calculating S=No-m/k, where No being a count of said second counter, making said register hold S, equalizing said number Nr for a next value to No and initializing the count No.
Claim 3
Dependent Claim
77 words
A digital frequency control circuit according to claim 1, wherein said calculation and control circuit comprises: a first calculating circuit calculating S=No-m/k; a second calculating circuit calculating Nr-S+m/k; and a control circuit, when said first counter have counted said number Nr of pulses, making said register hold an output of said first calculating circuit, equalizing said number Nr for said next value to an output of said second calculating circuit and clearing said second counter to 0.
Claim 4
Dependent Claim
139 words
A digital frequency control circuit for controlling in such a way that a frequency of an output signal of an oscillating circuit approaches a frequency of a reference signal, a pulse cycle T of said output signal being approximately a linear function of a control input value S, namely T=kS+m, comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said output signal as a feedback signal; a register holding said control input value S; a calculating circuit calculating S=No-m/k wherein No being a count of said second counter; and a control circuit, when said first counter have counted a number Nr of pulses, making said register hold an output of said calculating circuit, equalizing said number Nr for a next value to said count No and clearing said second counter to 0.
Claim 5
Dependent Claim
139 words
A digital frequency control circuit for controlling in such a way that a frequency of an output signal of an oscillating circuit approaches a frequency of a reference signal, a pulse cycle T of said output signal being approximately a linear function of a control input value S, namely T=kS+m, comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said output signal as a feedback signal; a register holding said control input value S; a calculating circuit calculating S=No-m/k wherein No being a count of said second counter; and a control circuit, when said first counter have counted a number Nr of pulses, making said register hold an output of said calculating circuit, equalizing said number Nr for a next value to said count No and clearing said second counter to 0.
Claim 6
Dependent Claim
133 words
A digital frequency control circuit for controlling in such a way that a frequency of an output signal of an oscillating circuit approaches a frequency of a reference signal, a pulse cycle T of said output signal being approximately a linear function of a control input value S, namely T=kS+m, comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said output signal as a feedback signal; a register holding said control input value S; a calculating circuit calculating Nr=S+m/k; and a control circuit, when said first counter have counted said number Nr of pulses, making said register hold a count of said second counter, equalizing said number Nr for a next value to an output of said calculating circuit and loading m/k to said second counter.
Claim 7
Dependent Claim
133 words
A digital frequency control circuit for controlling in such a way that a frequency of an output signal of an oscillating circuit approaches a frequency of a reference signal, a pulse cycle T of said output signal being approximately a linear function of a control input value S, namely T=kS+m, comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said output signal as a feedback signal; a register holding said control input value S; a calculating circuit calculating Nr=S+m/k; and a control circuit, when said first counter have counted said number Nr of pulses, making said register hold a count of said second counter, equalizing said number Nr for a next value to an output of said calculating circuit and loading m/k to said second counter.
Claim 8
Dependent Claim
51 words
A digital frequency control circuit according to claim 2, wherein: said first calculating circuit includes a buffer register for holding No; and said control circuit causes said first calculating circuit to execute calculations by making said buffer register hold No when said first counter has counted the number of Nr pulses.
Claim 9
Dependent Claim
51 words
A digital frequency control circuit according to claim 2, wherein: said second calculating circuit includes a buffer register for holding Nr; and said control circuit causes said second calculating circuit to execute calculations by making said buffer register hold Nr when said first counter has counted a number Nr of pulses.
Claim 10
Dependent Claim
65 words
A digital frequency control circuit according to claim 1, further comprising a convergence judging circuit judging whether or not said frequency of said feedback signal relative to a frequency of said reference signal has converged based upon an absolute value of a difference between an input value and an output value of said register when said first counter has counted said number Nr of pulses.
Claim 11
Dependent Claim
50 words
A digital frequency control circuit according to claim 1 wherein: said calculation and control circuit, when said first counter outputs a carry-out signal, calculates MAX-Nr, where MAX is a maximum count value of said first counter, and loads said first counter with MAX-Nr; and said first counter is an up-counter.
Claim 12
Dependent Claim
38 words
A digital frequency control circuit according to claim 1 wherein: said first counter comprises a down-counter; and said calculation and control circuit loads said first counter with No when a count of said first counter has reached 0.
Claim 13
Dependent Claim
136 words
A digital phase control circuit for controlling a phase error between a phase of an output signal of an oscillating circuit and a phase of a reference signal, a pulse cycle of said output signal being changed in response to a control input value S, said digital phase control circuit comprising: a phase comparator circuit judging a phase advance/delay of said output signal as a feedback signal relative to a phase of said reference signal; and a counter circuit counting up or down according to a result of a judgement by said phase comparator circuit and changing a count, when the result of the judgement has been reversed, to approximately an average value of first and last counts in previous successive same results of the judgements, said count being used as said control input value S.
Claim 14
Dependent Claim
136 words
A digital phase control circuit for controlling a phase error between a phase of an output signal of an oscillating circuit and a phase of a reference signal, a pulse cycle of said output signal being changed in response to a control input value S, said digital phase control circuit comprising: a phase comparator circuit judging a phase advance/delay of said output signal as a feedback signal relative to a phase of said reference signal; and a counter circuit counting up or down according to a result of a judgement by said phase comparator circuit and changing a count, when the result of the judgement has been reversed, to approximately an average value of first and last counts in previous successive same results of the judgements, said count being used as said control input value S.
Claim 15
Dependent Claim
65 words
A digital phase control circuit according to claim 10, wherein said phase comparator circuit judges the phase advance/delay of said feedback signal relative to said phase of said reference signal, with a timing of an edge of a pulse of either said reference signal or said feedback signal, by detecting a logical level of the other pulse of said reference signal and said feedback signal.
Claim 16
Dependent Claim
34 words
A digital phase control circuit according to claim 11, wherein said phase comparator circuit outputs a first pulse signal when said judgement is performed, outputs a status signal holding a result of said judgement.
Claim 17
Dependent Claim
116 words
A digital phase control circuit according to claim 12, wherein said counter circuit includes: a 1/2 frequency divider circuit having an input receiving said first pulse signal and having an output providing a second pulse signal; a first up/down counter having an up/down mode input receiving said status signal, having a clock input receiving said second pulse signal; and a second up/down counter having an up/down mode input receiving said status signal, having a clock input receiving said first pulse signal, having a load control input receiving a change pulse signal, having a parallel data input receiving a count of said first up/down counter and having a parallel data output providing said control input value S.
Claim 18
Dependent Claim
120 words
A digital PLL circuit, comprising: an oscillating circuit providing an output signal, a pulse cycle T of said output signal being changed in response to a control input value S; a phase comparator circuit judging a phase an advance/delay of said output signal as a feedback signal relative to a phase of a reference signal; and a counter circuit counting up or down according to a result of a judgement by said phase comparator circuit and changing a count, when the result of the judgement has been reversed, to a value that is approximately an average value of first and second counts in previous successive same results of the judgements, said count being used as said control input value S.
Claim 19
Dependent Claim
120 words
A digital PLL circuit, comprising: an oscillating circuit providing an output signal, a pulse cycle T of said output signal being changed in response to a control input value S; a phase comparator circuit judging a phase an advance/delay of said output signal as a feedback signal relative to a phase of a reference signal; and a counter circuit counting up or down according to a result of a judgement by said phase comparator circuit and changing a count, when the result of the judgement has been reversed, to a value that is approximately an average value of first and second counts in previous successive same results of the judgements, said count being used as said control input value S.
Claim 20
Dependent Claim
30 words
A digital PLL circuit according to claim 14, wherein said pulse cycle T of said output signal being approximately a linear function of said control input value S, namely T=kS+m.
Claim 21
Dependent Claim
129 words
A digital PLL circuit according to claim 15, further comprising: a first counter counting pulses of said reference signal; a second counter counting pulses of said feedback signal; a register holding said control input value S; a convergence judging circuit judging whether or not a frequency of said feedback signal relative to a frequency of said reference signal has converged; and a calculation and control circuit, when said first counter have counted a number Nr of pulses, making said register hold S=No-m/k, where No being a count number of said second counter and equalizing said number Nr for a next value to No, initializing the count No and selecting an output of said register as said control input value S before a convergence judgement of said frequency is made.
Claim 22
Dependent Claim
176 words
A digital PLL circuit, comprising: an oscillating circuit providing an output signal, a frequency of said output signal being changed in response to a control input value S; a digital frequency control circuit, providing a first control signal in response to said output signal and a reference signal, and controlling in such a way that said frequency of said output signal approaches a frequency of the reference signal; a frequency convergence judgement circuit judging a convergence of said first control signal; a phase comparator circuit judging advance/delay of a phase of said output signal relative to a phase of the reference signal; and a counter circuit counting up or down a count according to a judgement of said phase comparator circuit, said counter circuit providing said first control signal as said control input value S when said frequency convergence judgement circuit not judging said convergence of said first control signal, said counter providing said count as said control input value S after said frequency convergence judgement circuit having judged said convergence of said first control signal.
Claim 23
Dependent Claim
176 words
A digital PLL circuit, comprising: an oscillating circuit providing an output signal, a frequency of said output signal being changed in response to a control input value S; a digital frequency control circuit, providing a first control signal in response to said output signal and a reference signal, and controlling in such a way that said frequency of said output signal approaches a frequency of the reference signal; a frequency convergence judgement circuit judging a convergence of said first control signal; a phase comparator circuit judging advance/delay of a phase of said output signal relative to a phase of the reference signal; and a counter circuit counting up or down a count according to a judgement of said phase comparator circuit, said counter circuit providing said first control signal as said control input value S when said frequency convergence judgement circuit not judging said convergence of said first control signal, said counter providing said count as said control input value S after said frequency convergence judgement circuit having judged said convergence of said first control signal.
Claim 24
Dependent Claim
74 words
A semiconductor device, comprising: a first counter counting pulses of a reference signal; a second counter counting pulses of a feedback signal; a register holding a control input value S; and a calculation and control circuit, when said first counter have counted a number Nr of pulses, calculating S=No-m/k, where No being a count of said second counter, making said register hold S and equalizing said number Nr for a next value to No.
Claim 25
Dependent Claim
74 words
A semiconductor device, comprising: a first counter counting pulses of a reference signal; a second counter counting pulses of a feedback signal; a register holding a control input value S; and a calculation and control circuit, when said first counter have counted a number Nr of pulses, calculating S=No-m/k, where No being a count of said second counter, making said register hold S and equalizing said number Nr for a next value to No.
Claim 26
Dependent Claim
79 words
A semiconductor device, comprising: a phase comparator circuit judging a phase advance/delay of a feedback signal relative to a phase of a reference signal; and a counter circuit counting up or down according to a result of a judgement by said phase comparator circuit and changing a count, when the result of the judgement has been reversed, to a value that is approximately an average value of first and last counts in previous successive same results of the judgements.
Claim 27
Dependent Claim
79 words
A semiconductor device, comprising: a phase comparator circuit judging a phase advance/delay of a feedback signal relative to a phase of a reference signal; and a counter circuit counting up or down according to a result of a judgement by said phase comparator circuit and changing a count, when the result of the judgement has been reversed, to a value that is approximately an average value of first and last counts in previous successive same results of the judgements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |