US5399985A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital PLL circuit
Assignee: Fujitsu Ltd
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Filing: 1993-03-18
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Granted: 1995-03-21
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Expires: 2013-03-18
Abstract
Abstract The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error. A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator. The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them. A variable step number random walk filter is interposed between the phase comparator and the divider and has a selectively settable integration time constant, and an integration time constant setting circuit varies the step number of the random walk filter in accordance with information of a last phase controlling direction or directions and information of a phase controlling direction at present to vary the integration time constant of the random walk filter.
Inventors
- 👤 Yutaka Awata
- 👤 Nobukazu Koizumi
- 👤 Yasuo Ohtomo
- 👤 Mitsuo Kakuishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:40
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H03L7/10; H03L7/107; H03L7/1075
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
196 words
A digital PLL circuit, comprising: a master clock oscillator for oscillating a master clock signal having a frequency equal to N times the frequency of an input clock signal, N being an integral number; a variable dividing ratio divider for dividing the master clock signal received from said master clock oscillator by a dividing ratio which is normally equal to N, the dividing ratio of said divider being temporarily variable to another integral number around N; a phase comparator for comparing the phases of a division output of said divider and the input clock signal with each other; a variable step number random walk filter interposed between said phase comparator and said divider and having a selectively settable integration time constant for providing an output to temporarily vary the dividing ratio of said divider; and an integration time constant setting circuit, coupled to said random walk filter, for varying the step number of said random walk filter in accordance with information of the last phase controlling direction and information of a phase controlling direction at present obtained from the output of said random walk filter to vary the integration time constant of said random walk filter.
Claim 2
Dependent Claim
196 words
A digital PLL circuit, comprising: a master clock oscillator for oscillating a master clock signal having a frequency equal to N times the frequency of an input clock signal, N being an integral number; a variable dividing ratio divider for dividing the master clock signal received from said master clock oscillator by a dividing ratio which is normally equal to N, the dividing ratio of said divider being temporarily variable to another integral number around N; a phase comparator for comparing the phases of a division output of said divider and the input clock signal with each other; a variable step number random walk filter interposed between said phase comparator and said divider and having a selectively settable integration time constant for providing an output to temporarily vary the dividing ratio of said divider; and an integration time constant setting circuit, coupled to said random walk filter, for varying the step number of said random walk filter in accordance with information of the last phase controlling direction and information of a phase controlling direction at present obtained from the output of said random walk filter to vary the integration time constant of said random walk filter.
Claim 3
Dependent Claim
106 words
A digital PLL circuit as claimed in claim 1, wherein said integration time constant setting circuit determines whether or not information of a phase controlling direction in the last phase control cycle and said information of a phase controlling direction at present obtained from the output of said random walk filter coincide with each other and varies the step number of said random walk filter such that it decreases the step number when the information of the two phase controlling directions coincides with each other, but it increases the step number when the information of the two phase controlling directions does not coincide with each other.
Claim 4
Dependent Claim
157 words
A digital PLL circuit as claimed in claim 2, wherein said integration time constant setting circuit includes a coincidence detecting circuit for determining whether or not the information of the phase controlling direction in the last phase controlling cycle and said information of the phase controlling direction at present coincide with each other, and a bidirectional counter for outputting a controlling signal to said random walk filter to decrease the step number of the filter when said coincidence detecting circuit determines coincidence of the information of the phase controlling direction in the last phase controlling cycle and said information of the phase controlling direction at present but outputting another controlling signal to said random walk filter to increase the step number of the filter when said coincidence detecting circuit determines that the information of the phase controlling direction in the last phase controlling cycle does not coincide with said information of the phase controlling direction at present.
Claim 5
Dependent Claim
76 words
A digital PLL circuit as claimed in claim 1, wherein said integration time constant setting circuit takes the majority of information of a plurality of last phase controlling directions and said information of a phase controlling direction at present and varies the step number of said random walk filter such that it decreases the step number when the phase controlling directions are one-sided but increases the step number when the phase controlling directions are not one-sided.
Claim 6
Dependent Claim
158 words
A digital PLL circuit as claimed in claim 4, wherein said integration time constant setting circuit includes a shift register for storing information of a plurality of last phase controlling directions and said information of a phase controlling direction at present obtained from the output of said random walk fitter successively in a time series relationship therein, a majority circuit for taking the majority of the information of the plurality of last phase controlling directions and the information of the phase controlling direction at present based on an output of said shift register, and a bidirectional counter for outputting a controlling signal to said random walk filter to decrease the step number of the filter when said majority circuit determines that the phase controlling directions are one-sided but outputting another controlling signal to said random walk filter to increase the step number of the filter when said majority circuit determines that the phase controlling directions are not one-sided.
Claim 7
Dependent Claim
124 words
A digital PLL circuit as claimed in claim 5, wherein said majority circuit includes a cumulative adding circuit for cumulatively adding the information of the plurality of last phase controlling directions and said information of the phase controlling directions at said information of the phase controlling directions at present obtained from the output of said random walk filter successively stored in a time series relationship in said shift register to obtain integration information, and a judging circuit for judging from a result of calculation by said cumulative adding circuit whether or not the phase controlling directions are one-sided and for decrementing said bidirectional counter when the phase controlling directions are one-sided but incrementing the bidirectional counter when the phase controlling directions are not one-sided.
Claim 8
Dependent Claim
25 words
A digital PLL circuit as claimed in claim 1, wherein said random walk filter is formed as a bidirectional counter having a variable overflow value.
Claim 9
Dependent Claim
36 words
A digital PLL circuit as claimed in claim 1, wherein the dividing ratio of said variable dividing ratio divider is temporarily variable to N-1 or N+1 in response to the output of said random walk filter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |